SU1339549A1 - Device for rounding off sum and difference of binary-coded numbers with floating point - Google Patents

Abstract

The invention relates to digital computing and can be used in a digital computer to create high-precision arithmetic devices for adding and subtracting binary BaHiibix floating-point numbers presented in the reverse code. The purpose of the invention is to increase the accuracy of calculations. This goal is achieved by correcting both the denormalized term and the normalized result. Correction in each of these cases is affected by the forwarding of a digit or O, which is significant for the code, to the higher order of the corrected code. The significant digit in the lower order of the denormalized term is sent in case of at least one significant digit in the process of denormalization, and the significant digit in the lower order of the result is sent in the case of a significant digit rejection during normalization to the right. The device contains the result register 2, two triggers of 3, 4 characters, the inputs for control of denormalization 5 and normalization to the right 6, low bits 7, 8 of registers I and 2, two elements EXCLUSIVE OR 9, 10, four elements 11-14. I il. (C (L with so; about ate 4 with

Description

one

The invention relates to digital computing and can be used in a digital computer to create high-precision arithmetic devices for adding and subtracting floating-point binary numbers presented in a return code.

The purpose of the invention is to increase the accuracy of calculations.

The drawing shows the functional diagram of the device.

The device contains a register of 1 operand, a register of 2 results, triggers of 3 and 4 characters of a denormalizable number and a result, respectively, inputs 5 and 6 of the control of a normal normal and normalization to the right, minor bits 7 and 8 of registers 1 and 2, two elec

EXCLUSIVE OR 9 and 10 and four 20 are open or closed for

element and 11-14.

The device works as follows.

The rounding of the sum or difference of two floating point numbers represented in the reverse binary code is that both the denormalized term and the normalized result are corrected. The correction of a denormalized number is accomplished by sending a significant digit to its least significant bit, provided that in the denormalization process, at least one significant digit goes out of the register's output grid. Correction of a normalized number is accomplished by sending a significant digit to its least significant bit in the event that the result has been normalized to the right and beyond the register's register above the significant digit. The significant digit for a positive number in the reverse code is 1, and for a negative number is O.

Before the device starts operation, trigger 3 and register 1 are entered respectively with the sign and the mantissa of the term with a smaller order, and in case of equal numbers of orders, the sign and the mantissa of one of the components are entered.

If the order of numbers is different, then the code in register 1 is denormalized. Signal 1 is sent to the input of the right-shift control of this register, input 1 is sent, causing the code in register 1 to be shifted by one bit to the right. At the same time pushed beyond the limits of pe15

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Gistra junior bit disappears. Before i shift the code to the right, the signal from the output of the lower bit 7 of register 1 is fed to the input of the EXCLUSIVE OR 9 element, on the other input of which a signal from the output of the trigger 3 characters of the denormalizable number acts. As a result, the output of the EXCLUSIVE ALTER or 9 element is affected by a signal 1, if in the lower-order bit 7 of register 1 there is a significant figure, and O otherwise. This signal arrives at the first inputs of elements 11 and 12, on the third inputs of which signal 1 acts on input 5. Depending on whether a significant digit or not is in the low order 7 of register 1, elements 11 and 12 of the signal accumulation from direct and inverse, respectively, of outputs of trigger 3 to, respectively, zero and one input of the lowest bit 7.

Moreover, by the time of the arrival of the indicated signals at the inputs of the lower bit 7, this digit has a digit of the code already shifted by one digit to the right (to ensure this in the case of

the need for the lines connecting the outputs of the elements 1 and 12 with the inputs of the lower bit 7 must be supplied with the corresponding 1st delay elements). Thus, if an insignificant digit is found in the low-order bit of the 7 not yet shifted code, then the lower-digit digit of the code shifted by one bit to the right does not change, since O, O signals act at the inputs of the lower digits 7 If the register grid 1 is shifted to a significant digit, then the outputs of elements 11 and 12, depending on whether the number is normal or negative, have combinations of signals O. 1 or 1, O, which in the lower bit 7 are shifted by one p right to the code meaning significant qi Fru: 1 in the first case and

About - in the second. Thus, after the first exit for the bit grid of the register 1, the significant digit in the low-order bit 7 of this register for all

subsequent shifts of the code until the end of the denormalization will be a significant figure. This ensures the indicated correction of the denormalized number.

3

Next, the result of the addition or subtraction is normalized. The mantissa and zngk of the result are respectively in register 2 and trigger 4.

If the result is to be normalized to the right, then the input of the shift control to the right of register 2 to input 6 receives a signal 1, resulting in a shift of the code in register 2, one bit to the right. In this case, the low-order bit pushed out of the register disappears. Before the code is shifted, the output from the low-order bit 8 of register 2 is fed to the input of the EXCLUSIVE IPI 10 element, at another input of which a signal from the output of the trigger 4 of the result sign acts. As a result, the output of the EXCLUSIVE OR 10 element is a signal 1, if the digit 8 of the register 2 contains a significant digit in the m / d bit, and 0 otherwise. This signal arrives at the first inputs of elements And 13 and 14, on the third inputs of which a signal 1 acts, arriving at input 6. Depending on whether a significant or insignificant digit is in the low order of 8 registers 2, elements And 13 and 14 are open or closed for passing signals from the direct and inverse outputs of trigger 4, respectively, to the zero and single inputs of the low-order bit 8. Moreover, by the time these signals arrive at the low-level inputs 8, this digit has a figure already shifted by one n discharge right code (to provide that if necessary on lines connecting the outputs of AND gates 13 and 14 with the least significant bit input and 8, the respective delay elements to be delivered). Thus, if an insignificant digit is found in the low-order bit of the 8 still-shifted code, then the lower-digit digit of the code shifted by one bit to the right does not change, since O, O signals act on the low-level inputs 8. the bottom grid of register 2 is shifted to a significant figure, then the outputs of elements I3 and 14, depending on whether a positive or negative sign has the result, are combinations of signals O, 1, or 1, O, setting

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in the low order of 8, the result normalized to the right is a significant figure: 1 in the first case and O in the second. rum. Thus, after normalizing the result to the right in register 2, the binary code of the mantissa of the result corrected by the above method is found.

1Q Correction of the denormalized term and the result of the device leads to the fact that the rounding error may have different signs regardless of

15 is familiar in terms of the operation being performed. Indeed, let, for example, the magnitudes of the terms are such that normalization to the right of the result is not performed. In this case, the rounding error is the sum of the denormalization error associated with the rejection of the denormalized number of bits put forward beyond the discharge grid and the error associated with the sending of a significant

digits to the lower order of the denormalized number. Since the occurrence of a significant or insignificant digit in the lower order of a denormalized number is consistently reversed, sending a significant digit to this digit in half the cases gives an error other than zero, which in absolute value is greater than the error of denormalization and has

2g is the opposite sign. Thus, in half of the cases, the rounding error is positive, and in half of the cases - negative.

Expectation of error

40 rounding, arising from the operation of the proposed device, is strictly zero.

Claims (1)

Invention Formula 45 A device for rounding the sum and difference of binary-coded numbers with a floating point comma containing the operand register and the result register, 50 two sign triggers, wherein the shift control inputs of the operand register and the result register are connected to the denormalization control input and the normalization control input to the right of the device, respectively, characterized in that, in order to improve the accuracy of the calculations, it contains two EXCLUSIVE OR elements and four AND elements, where the low-order output of the register is connected to the first input of the first element of the primary or, the output of which is connected to the first inputs of the first and second elements AND, the outputs of which are connected to the zero and single inputs of the low bit of the operand register, the second inputs of the first element of the ICON SCHOOL OR, and The first element And is connected to the direct output of the first sign trigger, the inverse output of which is connected to the second input of the second element And, the third input of which is connected to the third input of the first element And and the input control denormalization device Editor E.Papp Order 4222/38 Compiled by O. Berezikova Tehred M. Hodaichkorrektor H, King Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Proizvodstp (. Ncho-polygraphic enterprise, Uzhgorod, Proektna st., 4 395A96 The normalization control input is connected to the right of the first inputs of the third and fourth AND elements, the outputs of which are connected to the zero and single inputs of the lower digit of the result register, the output of the lower bits of which is connected to the first input of the second element EXCLUSIVE OR, the output of which is connected to the second inputs of the third and the fourth element And, the third inputs of which are connected to the direct and inverse outputs of the second sign trigger, respectively, the direct output of which is connected to the second input of the second element (IC KEY OR. five ten 15