SU1361542A1 - Device for rounding off sum and difference of binary-coded numbers with floating point - Google Patents

Abstract

The invention relates to digital computing and can be used in digital computers to create high-precision arithmetic devices in addition and subtraction of binary-coded floating-point numbers presented in direct or additional code. The purpose of the invention is to improve the accuracy of calculations. The goal is achieved by correcting both the de-normalized term and the normalized result. Correction in each of these cases is carried out by sending the corrected code number 1 to the low-order bit. Link 1 to the lower category of the denormalized term is produced if at least one 1 is discarded in the process of denormalization, and sending 1 to the lower-order result - in the case of garbage at least one in the normalization process. The device contains a register of 1 operand, a register of result 2, inputs 3 and 4 of the control for denormalization and normalization to the right, lower-order bits of 5.6 registers, n-input elements OR 7 and 8, elements 9 and 10. 1 Il. sl vTn oe o :) ate 4 ;; go

Description

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The invention relates to digital computing and can be used in digital computers to create high-precision arithmetic devices by adding subtractions of binary-coded floating-point numbers presented in a forward or additional code.

The aim of the invention is to improve the accuracy of calculations.

The drawing shows a functional diagram of the device for the base of the H 16 number system.

The device contains the J one-15 rand register, the result register 2, inputs 3 and 4 of the control for denormalization and normalization to the right, the lower binary bits 5 and 6 of the register of the operand and the result register, two n-input elements SHSh 7. and 8 (n log N ) and two elements And 9 and 10.

The device works as follows.

The rounding of the sum or difference of two binary-coded floating point numbers with a base of 16, represented in a forward or supplemental binary code, is that

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the correction is made to both the denormalized term and the normalized result.

Moreover, in each of these cases, the correction is performed under the condition that the shift registers at least one digit 1 exit the discharge grid when the codes are shifted to the right and is performed by sending the digit 1 to be corrected in the lower order bit.

Before the device starts operation, register 1 contains the binary code of the term mantissa with a lower characteristic, and in the case when the characteristics of the numbers are equal, the code of the mantissa of one of the terms.

If the characteristics of numbers are different, then the code in register 1 is denormalized. To the right shift input of this register, control signal 3 receives a signal J, resulting in a code shift in register 1 by one tetrad to the right. When this is put forward, the tetrad disappears. The signals from the output of the bits of the lower tetrad of the code shifted in register 1 are fed to the inputs of the element OR 7, at the output of which the signal O acts, if in the lower tetrad the register

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Section 1 contains a zero code, and 1 if there is a J in one of the bits of this tetrad. Since the first input of the AND 9 element has a signal coming through input 3, then this element is open to pass the signal from the output of the OR 7 element to the lower bit 5, in which, by the time of arrival of the indicated signal, the digit of the code already shifted by one tetrad is set to the right (to ensure this, if necessary, a corresponding delay element must be placed on the line connecting the output of the And element to the lower bit 5) ). If in the lower tetrade of register 1 before the shift of the code there are zeros, then at the input 3 of the least significant bit after the shift of the code one tetrad to the right, the signal O acts, which does not change the state of this discharge. If in one of the bits of the lower tetrad of register 1 before the code shift there is at least one 1, then the younger bit 5 after the code shift will be in the state. Thus, after the first advancement of the digit grid of register 1 digit 1 in the lower bit 5 of this register, at all subsequent shifts, until the denormalization stops, the figure 1 will always be found. This ensures the specified correction of the denormalized number.

Next, normalization of the result of the operation is performed. The mantissa of the unnormalized result is in register 2. If the result is to be normalized to the right, then a signal is received at the input of the right-shift control of register 2 at input 4. 1, by which the binary code in register 2 is shifted by one notebook to the right. At the same time, the 2 tetrad fading out of the discharge grid of the register is lost. The signals from the outputs of the bits of the lower tetrad shifted in the register 2 of the code are sent to the inputs of the element OR 8, the output of which is a signal O, if the lower tetrad of register 2 contains a zero code, and 1 if in one of the bits of this tetrad has - g from 1. Since at the first input | of the element AND JO there is a signal 1, arriving at the input 4, this element is open for the signal to pass. from the output of the element OR 8 to the input jun5

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bit 6, in which by the time of arrival of the specified signal is set. a digit of the code already shifted to the right by one tetrad. If in the lower tetrade of register-2 there is a zero code to normalize the result to the right, then the younger digit of the shifted code is not corrected, since at the input of the lower digit 6 the signal O, not change, is in this case. If, when shifting to the right, for the bit grid of register 2, 1 is pushed, then signal 1 is received at the input of the least significant bit 6, as a result of which the specified bit is set to state 1. This ensures the specified correction of the normalized result.

The rounding carried out by the device leads to the fact that the rounding error may have different signs, regardless of the signs of the numbers of the type of code in which they are. presented, and the operation being performed. Indeed, let, for example, the magnitudes of the terms are such that normalization to the right of the result is not carried out. In this case, the rounding error is the result of the denormalization error of one of the addends associated with dropping the bits of the denormalized number put forward for the discharge grid and the error associated with sending J to the least significant bit of the denormalized number. Since the occurrence of the digit O or in the decimal digit of the de-normalized term is equal, the sending of the digit 1 in this digit gives an error in half of the cases different from zero, which in absolute value is greater than the error of

Editor V. Bugrenkova

6291/48

Circulation 671 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, Projecto st., 4

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normalization and has the opposite sign. Thus, in half of the cases, the rounding error is positive, and in half of the cases - negative.

The mathematical expectation of the error of rounding that occurs during the operation of the proposed device is strictly zero.

Claims (1)

Invention Formula A device for rounding the sum and difference of binary-coded floating point numbers containing the operand register and the result register, the right shift input for n bits (n log N, Ы - the base of the number system) of the operand register and the result register are connected respectively to the input control de-normalization and input normalization control to the right of the device, characterized in that, in order to increase the accuracy of calculations, it contains two p-input OR elements and two AND elements, and the inputs of n bit bits The operand and result registers are connected respectively to the inputs of the first and second p-input elements OR, the outputs of which are connected to the first inputs of the first and second elements AND, the second inputs of which are connected to the denormalization control input and the normalization control input to the right of the device, the outputs of the first and second elements And are connected to the inputs of the lower binary bits, respectively, of the operand register and the result register. Compiled by O. Berezikova Tehred A. Kravchuk Proofreader A. Zimokosov