SU1413617A1 - Device for collecting and preprocessing information - Google Patents

Description

(21) 4176158 / 24-24

(22) 01/06/87

(46) 07/30/88. Bul Number 28

(71) Production Association Krasnodar ZIP

(72) D, B. Vioensky

(53) 681.327 (088.8)

(56) USSR Author's Certificate No. 1012230, cl. G 06 F 3/00, 1981.

USSR Author's Certificate No. 448458, cl. G 06 F 3/00, 1973.

(54) DEVICE FOR COLLECTION AND PRELIMINARY PROCESSING OF INFORMATION

(57) The invention relates to information-measuring and computing technology. The aim of the invention is to accelerate the detection of number-pulse signals. The device contains n inputs of pulse signals, a buffer drive, first, second and third counters, a control register, first and second decoders, first, second, third and fourth elements of the STI, pulse generator, first, second, third, fourth and fifth delay elements, n buffer triggers, a group of elements AND, element I. The application of the invention frees up the useful processor time and increases the reliability of recording the number of pulse signals. 2 Il.

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The invention of :-. Ts to information and measure. Gtnzh and computing,

The purpose of the invention is to increase the speed of the register of a number of pulses of signals, the reliability of their registration by counting the number of pulses by the hardware of the device itself.

Fig „1 shows the scheme of the device; figure 2 - timing charts of the device, where a) - the pulses at the output of the generator 8; b) - pulses at the second output of the decoder 6 c) - signals at the output of the element OR 12 (signals from the buffer accumulator), d) signals at the counting input of the 4-address counter; e) signals at the output of the delay element 24 (signals for polling the state of the 17p triggers) 5 e) signals at the output of the delay element 20 (recording signals to the buffer store).

The device contains: n inputs 1 pulse signals, buffer storage 2, first counter 3, second counter 4, control register 5 5 first decoder 6, first element OR 7, pulse generator 8, third counter 9, second element Ш Ш ТО, first element 11 delays, third element OR 12, information output device 13, device readiness output 14, AND 15 element, device operation mode input 16, n buffer triggers 17, AND 18 group of elements, second decoder 19, second delay element 20, third element 21 delays, fourth element 22 delays and, the fourth element OR 23, the fifth element 24 delay.

The device operates in three pe) f (im 1 is the mode of cleaning the buffer accumulator; 2 is the mode of polling the sensors and counting the number of pulse signals, 3 is the mode of transmitting information located in the buffer accumulator to the calculator.

The mode number is entered into the control register 5 from the calculator (not shown). Simultaneously with the setting of the mode number, the counters 3,4 and 9 are reset, the Depot 6 has a control input to which the square pulses are received from the 8 generator. the output of the decoder 6, the signals corresponding to the states of the register 5, appear in

the operating time of g-generator impulses 8. i.e. gating is performed. The first mode, B of the control register 5 is entered into binary code 11. The signal from the corresponding year of the descriptor 6 through the element OR 7 sets the counter of 4 addresses to the first position. The signal from the output of the element OR 23, delayed by the delay element 20 at the recalculation time counter 4, enters the buffer storage as a write signal. The data written to the buffer is in

counter 3, which is set to zero, therefore, the buffer storage cells are cleared.

Recalculation of the counter of 4 addresses occurs for each generator pulse

8. After installing all bits

the counter 4 in the single state triggers the element AND 15, the opening of which is prepared by the single state of the second bit of the register 5, and the signal from the output of the element 15 And the register 5 is reset to This completes the operation of the device in this mode.

The second mode, In the control register

The code 0.1 is entered. The impulse from the output of the decoder 6 corresponding to this mode (output denoted by 01), through the element OR 7, sets in the first state the counter of 4 addresses

and counter 9. For the same pulse, through the delay element 11, which provides a delay for the time it takes to recalculate counter 4, the buffer cell is read through the OR element 12.

accumulator 2 and entering a cell with a parallel code in counter 3, the signal from the decoder 19 opens an AND 18 element corresponding to

the first of the n sensors, the number of pulse signals from which 3 corresponding triggers 17, + 17, are memorized

The signal from the output of the delay element 24, which is delayed by the recalculation time of the counter 9, ensures that the signal passes through the AND 18 elements. If by the time a signal appears at the gate input of the And 18 element, the first trigger in the trigger group 17 is in one state, the output signal of the element HTDi 10 increases the content of counter 3 by one, t, e, and the summation

pulse signals on i sensor.

The output signal of the AND 18 register 17 is reset to the zero state. The signal from the output of the delay element 11 passes through the OR element 23, is delayed by the delay element 20 by the time taken to read the cell of the buffer accumulator 2 and the unit's cumming in counter 3, and enters the buffer memory 2 as a recording signal. In this case, the data of the counter 3 with a parallel code is written into the cell at the address determined by the short code 4.

The next pulse from the output of the generator 8 is recalculated into a unit of the address 4 and the counter 9. Similarly, the number of pulses in the cell of the buffer storage 2 corresponding to the second sensor is summed from -. sensor groups. After polling the last trigger in the group of n triggers 17, counters 4 and 9 are set to the states corresponding to the poll of the first trigger, and the polling cycle of the entire group of triggers 17 is repeated. These cycles are repeated until the corresponding mode is set in register 5.

The full and; interrogation of the sensors is equal to Tc T, where T is the frequency of the generator 8, determined by the duration of the read-write operations of the buffer accumulator and the recalculation of counters 3 and 4 The device provides a reliable recording of the number of impulse signals whose frequency is received by each / ad sensor f;; those. device speed depends only on speed

elements used and the number of inputs.

The third mode. In the control register 5, the binary mode mode code 10 is entered. The signal from the corresponding output of the decoder 6 (output 10) through the CM 7 element sets the counter 4 to the first state and, passing through the delay element 21, providing a delay for the counter recalculation time 4, and the element OR 12 enters buffer storage 2 as a read signal.

The data from the buffer accumulator 2 by the parallel code is transferred to the counter 3. According to the screen from the output of the element

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0

five

0

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The time required for the data from the buffer accumulator 2 and entering it into the counter 3, dn1 1e from the output 13 is sensed by the calculator,

On the next impulse from the generator 8, the counter of 4 addresses is recalculated and data is read at the following address from the buffer accumulator 3 and transferred to the calculator.

After setting all the bits of the counter 4 to one, the AND 15 circuit is opened, prepared for triggering with the single signal of the second bit of register 5, and the signal from the output of the AND 15 element resets the control register 5 to the zero state. This mode of operation ends there.

Thus, in the proposed device, an effect is achieved that cannot be obtained in similar devices. The proposed device allows for the input of information from a number of users and to calculate the number and number of pulses5 received from each sensor during their cyclic polling. Thanks to hardware analysis of the number of pulses, there is no need to analyze the appearance of the signal by the sensor at the sensor and, if it exists, communicate with the calculator to transmit one bit of information. The device achieves an additional effect, associated with an increase in its speed due to the subcharacterization of pulses by hardware without the involvement of a calculator operating according to the appropriate program and, as a result, reliability is increased, since at a high polling rate of the state of the triggers 17 impulse before the previous pulse registered in the corresponding trigger trigger,; will be identified and summarized in the corresponding cell of the buffer opitel.

Claims (1)

Invention Formula A device for collecting and pre-processing information, 1; c; i.4pp, buffered buffer triggers, the installed inputs of which are format: P (- the inputs of the device are set to -.t71a, the per- cent estimates5U1 chick, different; that, in order to increase the speed of registration of pulse-counting signals, i a group of elements I, I, second and third counters, buffer I drive, first and second decoders, control register, pulse generator I, elements I, first, second, i the third and fourth elements OR, the first, second, third, fourth and fifth delay elements, the first inputs of the group of elements And are connected to the outputs of the corresponding buffer I flip-flops, the second inputs of the group of elements I And are connected to the corresponding I outputs of the second decipher Ator, whose inputs are connected to the outputs of the third I counter, the clock input of which is connected to the input of the first and fifth delay elements, the second output I of the first decoder and the second input of the first OR element, the first input of the iKoToporo is connected to the third output of the first decoder and input The third delay element, the output of which is connected to the first input of the third OR element and the fourth delay element input, the output of which is with the device ready output, the second input of the third OR element is connected to the output of the first ementa delay and the first input of the fourth OR gate, a second input coupled to the first output of the first decoder and the third input of the first - ten 15 36176 the OR element, the output of which is connected to the clock input of the second counter, the first output of which is connected to the first input of the buffer accumulator, the second output of the second counter is connected to the first input of the AND element, the second input of which is connected to the first input of the first decoder and the second output of the control register, the first output which is connected to the second input of the first decoder, the first input of the control register is the input of the operating mode of the device, and the second input is connected to: the output of the And element, the second input of the buffer storage device the third input of the buffer accumulator is connected to the output of the second delay element, whose input is connected to the output of the fourth OR element, the fourth input of the buffer accumulator is connected to the output of the first counter and is the information output of the device, the output of the buffer accumulator is connected to the second input of the first counter, the first input of which is connected to the output of the second element OR, whose inputs are connected to the outputs of elements AND of the group and the reset inputs of the corresponding buffer trigger , The third inputs of the group of AND gates connected to the output of the fifth delay element, a third input of the first decoder connected to the output of the pulse generator. 20 25 thirty 35 P l P. l FIG. 2