SU1399723A1 - Digital function generator - Google Patents

Abstract

The invention relates to computing technology, is intended to generate codes for digital values of functions at discrete equal-time points, and can be used in simulation and half-track modeling systems to differentiate input signals. The purpose of the invention is to enhance the functionality by generating a non-periodic function and a periodic function with multiple maximum values. The generator contains an element I 1, a trigger 2, a delay element 3, a counter 4, a control memory block 5, a computing unit 6, a memory block 7, a multiplier 8, a clock input 9, a first 10, a second 11 information inputs, a control input 12, first 13, second 14 control outputs information outputs 15. The purpose of the invention is achieved by the introduction of a computing unit 6, a control memory block 5, a memory block 7 and a multiplier 8. 1 Il. (L

Description

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funktsi} 1alpiko; s mozhey geyier Tojj | a due to the generation of aperiodic function and 1eris; a set of m maximum values °.

: The drawing shows the structural scheme of the hegerator,

The generator contains an Element I 1, a trigger 2, a delay element 3, a counting 4, a bl} with 5 control,

read New block b, block 7 to us; Smart Zglglt 8 ,, input 9 clock pulses, first 10 and second 1 information OH ijbie inputs 3 control input 2, first 13 l second 14 control outputs and signals. exits 5.

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jllo signal initial setup

(n (shown) trigger 2 is set ij; unit, sastoi. by which the ID counter D is written gigachal iri);, rep blocks 5 and 7. If No npHteuaica KOH1U1 of period5 from the block stroke: 5 at the input of the element H 1 post cnijjian chulevogo level. With postullepia | of the first TM pulse but bus 9 trig ger | 2 ustanag. It is a zero sos (at the output of the element And J is not present. And it is a level), allowing the operation of counter 4 in the counting mode, PeregdniG; the front of the clock from the bus 9 increases the –A and the content of the counter j, which enters 5; and the inputs of the block 5 and the input 6, the Math ii (read control signals do not) go to second G1 informadio. inputs of the computing unit 6. At the same time, the control inputs B1g of the numeral block 6 are received by the network: Logs from the block 5. In block 6, the forg addresses of block 7 from the current address (counter 4 output) and address from block 5 are received At the address of the numeral unit bz of block 1, information is read (ciirnajro; control with blocking

7 not shown). On the multiplier 8, the information read from the block 7 is multiplied by the value of the aptlite fed on input 11. At the end of the period of the generated function from block 5, the lower information level reads the unit level which goes to one of the inputs of the I element 1. If necessary process generation, i.e. extending the function period, input 12 receives a logical zero level which blocks the end of period signal. If it is necessary to work with a predetermined period or to change the initial phase of the generated function, input 12 receives a logical unit signal, which by the next clock pulse is written to trigger 2, whose single output writes 4 information from inputs 10 to counter 4.

Claims (1)

The delay element 3 serves to keep the counter 4 running in the liver in the counting mode B, the period of switching trigger 2 from one to zero. The signal at output 13 indicates to the processing device (not shown) the moment of reading information from outputs 15. The signal at output 4 indicates to the processing device at end of period of the generated function. Invention Formula A digital function generator, an And element, a counter, a memory unit, a multiplier, and the memory unit output is connected to the first information input of the multiplier, so that, in order to extend the functionality by generating a non-periodic function and a periodic function with a set of maximum values, introduced a delay element, a trigger, a control memory block and a computing unit, the input of the delay element and the trigger synchronization input are connected to the generator clock input, the start input values - the addresses of which are connected to the data input of the counter, the setup input of which is connected to the output of the trigger, the data input of which is connected to the output of the And element, the first input of which is connected to the INPUT of the blocking sign of the end of the generator period, the amplitude input of which is connected to 31399723, the second information input of the CENTRAL series of which is connected to the second ID the inhabitant, the output of the delay element to the subformation input of the computational key to the counting input of the counter of the unit, whose control input to the output gate of the tracking strobe of the general key to the output (kl) of the bits of the torus, the information output of the control memory, the output of the multiplier, the output of which is connected to the second counter is connected to the first and -for input of the AND element and the output of the sign to the computing input of the computational terminal of the generator period, the output of the computation and the address input of the control unit Call duration unit is connected to the conductive Location- memory output older (n-k) time-Term entry memory block.