SU1391614A1 - Apparatus for measuring pulse rate - Google Patents

Description

G21) 3905887 / 28-1

(22) 07.06.85

(46) 04/30/88. Bul Number 16

(71) Institute of Physics of the Academy of Sciences of the BSSR and Minsk State Medical Institute

(72) B.V. Obolonkin, A.S. Naumovich, G.K. Ilyich, A.V. Kireev and I.A. Karpovich

(53) 615.475 (088.8)

(56) U.S. Patent 4,331,154,. cl. A 61 B 5/02, 1982.

(54) DEVICE FOR MEASURING PULSE FREQUENCY

(57) The device for measuring the pulse rate contains sequences; connected sensor 1 of cardio pulses amplitude selector 2, counter 3 pulses, block 4 of memory, register 5 and block 6 of indication. In order to reduce power consumption by decreasing the information capacity of the memory block, an 11PI-NOT element is inserted into it, to which the high-order bits of the output of the counter 3 and mylvs are connected to the input, and the output of the register-5 to the most significant bits of the input to the entry of the register 5. 1 Il.

with so

O5 4:

The invention of medical science and technology can be used in systems for monitoring the state of the cardiovascular system.

The purpose of the invention is to reduce oner consumption by reducing the information capacity of the memory bypass.

AND;; The diagram shows the structural scheme of the device.

The device for measuring the pulse rate contains a sensor 1 FM card pulses, an amplitude selector 2, a counter 3 pulses, a block 4 of memory, a register 5, a block 6 of indication, a generator of pulses 7, the element 8 MLI-HE.

The device works as follows: -KJM.

The measurement cycle starts from the arrival of the mouth amplitude selector 2 imp / s from sensor I cardio pulse CO13, which are then amplified, normalized in amplitude and duration illo to the falling edge of the pulse. The counter 3 pulses is set to the O state. The clock pulses of the oscillator 7 of the pulses change the state of the outputs of the pulse counter 3 and at the outputs of the memory block 4, made, for example, on the basis of a permanent memory (ROM), appears the entire word written at the address corresponding to the content of the counter 3 pulses at the moment.

The senior four bits of the binary-decimal code of this word define tens, the remaining four bits - units of frequency value.

The programming of the address in the ROM containing the frequency value is carried out according to the formula ,, 60-f

s ---,

de F - heart rate 1 / min;

f - oscillator frequency 7, Hz; n is the content of a cut-off 3. The conversion of a reference, proportional to the period of cardio pulses, into a number equal to the frequency value is carried out in accordance with the expression

, t-k

f 0, 6

where f is the frequency of the generator 7, Hz; t is the number of bits of counter 3;

0

five

k is the number of high bits of the counter 3 connected to the inputs of element 8 OR-NOT; 0.6 is the period of cardio pulses corresponding to a frequency of 100 min.

On the front of the next pulse arriving from the input of the amplitude selector 2, the information present on the information inputs of the register 5 will be fixed in it and the corresponding signal on it will go on its outputs. If by the time of the arrival of the front of the subsequent pulse from amplitude selekto.ktor 2 the contents of the counter 3 pulses exceed the value of p., Corresponding to 100 beats per 1 min, 14) in register 5 together with the word present at this moment at the output of memory 4, Records O at a location corresponding to hundreds of heart rates. It will happen because at p) p, oo at least one of the most significant bits of the counter 3 pulses is set to 1 and at the output of element 8 OR NOT

thirty

35

there is

 ABOUT

Vice versa at

on

the output of the element 8 OR-PE is 1. The codes from register 5 control the display unit 6. Upon the arrival of the trailing edge of the pulse from the amplitude selector 2, the pulse counter 3 is set to O and the measurement cycle is repeated.

Claims (1)

Invention Formula A device for measuring the pulse rate, containing serially connected cardio pulses, an amplitude selector, a pulse counter, a memory unit, a register and a display unit, a pulse generator connected to the second pulse counter input, in order to reduce energy consumption by reducing information the capacity of the memory block, an OR-NOT element is entered into it, the high-order bits of the output of the pulse counter are connected to the input, and the output is connected to the high-level bits of the register input, the output of the amplitude select pa podklyucheN1 to register record entry.