SU1387005A1 - Data input device - Google Patents

Abstract

The invention relates to automation and computing and can be used in control and monitoring systems for inputting information from discrete sensors. The purpose of the invention is to increase the reliability of the input information. The device contains pulse selectors 1, multiplexers 2, 3, 4, matching elements 5, elements OR-NOT 6, 7, 8, 9, 10, 11, 26, decoder 14, counters 12, 15, 27 and 28, elements AND- NOT 17 and 18, triggers 22, 23, 24 and 25, elements NOT 19, 20, 21, sensors 13. The introduction of pulse selectors 1 and matching elements 5 provides filtering of bounce type signals, as well as protection against general type noise. The entries entered allow the information from the sensors 13 to be packed into consecutive 32-bit words with a parity check of each transmitted word and transmitted to the line with a bipolar code. 1 il. (

Description

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The invention relates to automation and computing and can be used in control and monitoring systems for inputting information from discrete sensors.

The aim of the invention is to increase the reliability of the input information.

The drawing shows a block diagram of the device.

The device for entering information contains selectors 1 pulses in duration, first 2, second 3 and third 4 multiplexers, matching elements 5, elements OR NOT 6-11, first counter 12, sensor 13, decoder 14, third counter 15, pulse generator 16 , elements AND-NOT 17 and 18, elements NOT 19-21, triggers 22-24, counting trigger 25, element OR-NOT 26, second 27 and fourth 28 counters.

Each of the pulse selectors 1 consists of an integrating circuit R2C1 and a Schmitt trigger made on the operational amplifier D1, covered by positive feedback resistors R5 and R6. The selection time in terms of duration is determined by the time constant of the integrating circuit R2C1 and the trigger thresholds of the Schmitt trigger, which are determined by the ratios of the resistors R5 and R6. As a D1 power amplifier, you can use any opamp capable of being powered by a unipolar source. The diode VI serves to limit the level of the signal entering the integrating circuit at a level, and the level of the signal from the sensors 13 must be higher than + Un of the selectors 1 of the pulses. The diode V2 serves to protect the filters from surges of negative polarity voltages at their inputs. The resistor also serves to limit the current through diodes VI and V2. The resistor also serves to enable the operation of selectors of 1 pulses from signals of the type +27 V - an open circuit. Matching elements 5 consist of a Kth number of optocouplers with a control circuit.

The device works as follows.

In the initial state, the triggers 22 and 25 are in the state "O, the triggers 23 and 24 are in the state" 1, the counter 12 addresses the interrogated sensors 13 and the generated consecutive words, the counter 15 is zeroed. Each of the sensors 13 is connected to its own pulse selector 1, which constantly monitors the state of the output signal of this sensor, and a signal that does not change its value over time is considered reliable. This is because the voltage across capacitor C1 cannot change abruptly. For example, when the signal

at the output of the sensor 13 of the form (break -Ue.c.)

this voltage varies with constant

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time R2C1 to the upper trigger threshold of the Schmitt trigger, performed on the operational amplifier D1, covered by the positive feedback by the resistors R5 and R6. When the voltage across this capacitor exceeds the upper Schmitt trigger threshold, the voltage at the output of the operational amplifier D1 changes abruptly and thereby lowers the trigger threshold. Consequently, the pulse selector 1 is absolutely insensitive to contact sensor bounce 13, since capacitor C1 cannot discharge discharged to the lower threshold of operation, and discharges from time constant C1 (R2 + + R4) H (R3 + RBx.p). In this scheme, diode VI serves to limit signals from sensors 13 at the level of -f-Un, diode V2 protects the circuit from voltage spikes of negative polarity. The pulse selector 1 is powered by a unipolar power supply with an artificially created midpoint to which it is connected by a resistor.

R6. The elements are selected in such a way that the on-off and on-off signal delays are approximately the same.

Based on the specified initial static position, it follows that the logical signal "O from the direct output of the trigger 22 first counter 12 at the C-input is blocked, the fourth counter 28 to the C input is blocked by the level of the logical" O from the inverse output of the trigger 24, the third counter 15 is unlocked for C pulse counting by logic level “1 from the output of the OR-NOT 8 element, at two inputs of which the logic level“ O ”is set. At the same time, the signal from the output of the element OR NOT 8, through the element NOT 20, arriving at the V-input of multiplexer 3, removes the lock from it, and also, arriving at the second input of the element OR-NOT 11, permits the passage of signals through it from the multiplexer 3. Change the state of the third counter 15 occurs on the leading edge of the pulses arriving at its input from the output of the HE element 21, therefore, after the C input of the counter 15, the signal changes its state from the logical level "O to logic level" 1 to input element is NOT 21 half level period logical zero, which is set at the output of the second element AND-NOT 17 logic level "1, which, having entered the A1 input of the address input of the multiplexer 4, depending on the voltage level at the AO input, turns on the XZ-X, Y3-Y or X4-X, Y4-U, and since the inputs X3, X4, UZ, U4 are connected to the neutral wire, then on the outputs X and Y the level “O. During this half period, all transients inside the circuit end and no interference occurs at the output. Code number.

counted by the third counter 15, arriving at the address input of multiplexer 3, turns on all its channels from XI to X8 in turn, in which the inputs of the XI-X3 receive the address part of consecutive words formed by the second counter 27, and the input X8 - the parity information transmitted consecutive words, which is carried out by the trigger 25. However, at this point in time, the output signal is that which corresponds to the address generated from catch, since the address code goes to the decoder 14, the output signal of which through matching elements is 5 o uniquely determines the portion of the multiplexer 2 which must work at the moment. When polling any 16 sensors 13 at the second input of the element OR NOT 6, a logical level of "O is specified, which resolves the passage through this element, as well as through

trigger cannot pass through element 10 OR-NOT 26 (as at the first, ment OR-NOT 10, because at its first third and fourth inputs is set

the input establishes the logical level level of the logical "O) to the AO input of the multiples 1, therefore, at the input X8 of the multiplexer 4, information about the status of the onsoror 3, the level of the logical O. The signal from the sewn-in sensors which

the course of this multi-multiplexer, nroyd through ,, the entry of the element OR NOT 6 comes through

matching elements 5 from the output of multiplexer 2. Depending on the level of the signal elements OR-NOT 11 and OR-NOT 26, since the remaining inputs of the inputs have logical levels “O, goes to the AO-input of the multiplexer 4, and in that part of the pulse period with generator 16 is impulse at the AO input of multiplexer 4 at its outputs X and Y, we obtain bipolar antiphase signals gated with

when the A1 input is a logic level with 20 pulses of the generator 16 pulses. After “O, depending on whether, at the AO input, the logical level is“ 1 or “O, on the X input, the signal is respectively either -f-Un or -Un, and at the Y-output or -LJn, either. When the logical level "1" appears in the fourth bit of the third counter 15, then the logical element "O, which, having passed through the element 19, is inverted, appears at the output of the element OR, and, arriving at the R input, resets all bits of the third counter 15 in “O”, after which the logical level “1, i.e. at the output of this element at this moment in time, a short pulse appears, the levels of which change in the following sequence: logic level "1 - logic level" O - logic level "1. And since the output of this element is connected to the C-input of the trigger 22, the voltage drop from “O to” 1 it changes its state and the logic level “1” from its direct output removes the counting lock on the C input from the first counter 12, and also, arriving at the first inlet, the element OR-NOT 8, sets at its output the logical level “O”, which blocks the C-wicked account as the first counter 12 reaches 16 (i.e., a certain group of 16 sensors 13 are polled) , the back of the pulse with "1 in" Oh, in the second counter 27 is recorded logical "1 (i.e. prepared The next address of the word and, accordingly, the next group of sensors 13), the same pulse front, passed through the element OR NOT 7, is inverted and, arriving at the C input of the trigger 23, sets this trigger to the state "O, since The D input at this point in time is a logical level "O, the trigger 22 is set to the same state. The logical level" O from the direct output of the trigger 22 is blocked by the first counter 12, and the logical level "1 from the inverse output of this trigger is blocked - the signal from the output of multiplexer 2 through the element OR is NOT 6, and the second counter 27 is also blocked. At the same time point, the output level of the OR OR NO 8 element is a logical level of "1 (since

40 two of its inputs set the logical levels “O), which allows the counting at the C-input of the third counter 15, as well as inverted, traversed the element NOT 20, removes the blocking from the multiplexer 3 and permits the passage of the signal from the output

do the third counter 15 and pass through the 45 multiplexer 3 through the element OR NOT

the ment is NOT 20, the level of logic "1 blocks multiplexer 3 and the element OR-NOT 11. At this time, the inverse output of the trigger 22 sets the level of the logic" O, which will remove

11, but prohibits the further passage of this signal from the first four addresses (XI-X4) through the element OR-NOT 26, since at this time on the third and fourth inputs of this element by the element OR-NOT

the blocking of the account at the CE input of the second account is set to 9 logical level "1,

27, performing the counting on the falling edge of the incoming pulses. The first counter 12 counts up to 16, which corresponds to the number of bits of the information part of the sequential code. A code of numbers from 0 to 15 through matching elements 5, arriving at the address input of multiplexer 2, performs a sequential interrogation of those 16 sensors 13, which are

in view of the presence at its inputs of the logical level “O. From the fifth address to the eighth signal from the output of the multiplexer 3 freely passes to the AO input of the multiplexer 4 with its further conversion by it, indicated earlier. For parity, the signal from the output of the element OR NOT 26 arrives at the first input of the element AND NOT 18, the second input of which enters the clock parts corresponding to the address formed from the catch, since the address code goes to the decoder 14, the output of which through the matching elements 5 uniquely identifies the part of multiplexer 2 that should be operating at the moment. When polling any 16 sensors 13 at the second input of the element OR NOT 6, a logical level of "O is specified, which resolves the passage through this element, as well as through

the element OR NOT 26 (since the first, third and fourth inputs are set

matching elements 5 from the output of multiplexer 2. Depending on the signal level at the AO input of multiplexer 4 at its outputs X and Y, we obtain bipolar out-of-phase signals gated by pulses of the generator 16 pulses. After 0

0 pulses of the generator 16 pulses. After the first counter 12 reaches 16 (i.e., a defined group of 16 sensors 13 has been polled), the back edge of the pulse from "1 to" O, the logical counter "1 (the new address of the layer and respectively, the next group of sensors 13 is selected; the same pulse front, having passed through the element OR NONE 7, is inverted and, arriving at the C input of the trigger 23, sets this trigger to the “O” state, since at its D input this moment of time the logic level "Oh, the trigger 22 is set up in the same state. The logic level" About direct output trigger 22, the first counter 12 is blocked, and the logic level "1 inverse output of this trigger blocks the passage of the signal from the output of multiplexer 2 through the element OR NOT 6, and also blocks the second counter 27. At the same time point at the output element OR - NOT 8 appears logical level "1 (since

0 its two inputs set the logical levels “O), which enables the counting at the C input of the third counter 15, as well as inverted, traversed the element NOT 20, removes the blocking from the multiplexer 3 and allows the output signal to pass

5 multiplexer 3 through the element OR NOT

 multiplexer 3 through the element OR NOT

11, but prohibits the further passage of this signal from the first four addresses (XI-X4) through the element OR-NOT 26, since at this time on the third and fourth inputs of this element by the element OR-NOT

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in view of the presence at its inputs of the logical level “O. From the fifth address to the eighth signal from the output of the multiplexer 3 freely passes to the AO input of the multiplexer 4 with its further conversion by it, indicated earlier. For parity control, the signal from the output of the element OR-NOT 26 is fed to the first input of the element AND-NOT 18, the second input of which receives the clock frequency from the generator of 16 pulses, interrupting the signal received at the first input of the element, with further parity trigger 25 operating in counting mode, a direct output connected to the X8 input of multiplexer 3 via an OR-NOT 10 element, the first input of which receives a logic level “O from the direct output of trigger 23. When the fourth discharge of the third counter 15 is ow mc level "1 (which corresponds to the number eight written in it) at the output of the element OR NOT 7 sets the logical level" O. This signal, having passed through the element NOT 19, is inverted by it and sets the counter 15 to the state "O", after which the logical level "1 appears at the output of the element OR NOT 7. The voltage drop from the logic level "O to the logic level" 1 at the output of this element sets the trigger 23 to the state "1, because at this moment of time at its D input the logic level is" 1, and the voltage drop from the logic level " About to the logical level “1 from its direct output, trigger 24 - to the state“ O. The logic level “О from the direct output of this trigger sets the output logic level“ 1 ”at the output of the NAND 17 element, which sets the output level“ O ”at the X and Y output of the multiplexer 4. The logical level "1 inverse output of this trigger sets to the state" On trigger 25 (performing parity) and removes the blocking of the counting from the C input of the fourth counter 28. When in the third bit of this counter appears the logical level "1, which corresponds to the four periods of pulses from the pulse generator 16, the trigger 24 by this voltage level is set to state "1", which corresponds to the initial state, and the cycle is again repeated around the ring.

Thus, at the output of multiplexer 4, a 32-bit serial bipolar code is obtained, in which bits 1-8 are the address of the word, bits 9-24 are informational words, bits 25-31 are zero, bit 32 is the control parity, bits 1-4 - pause.

After each transmission cycle of the information about the next 16 sensors 13, the address of the second counter 27 changes to 1. Therefore, when it counts eight addresses, by the ninth it is reset to “O, because in this case the fourth output is is the logical level "1, which arrives at its installation R input, after which the counting of addresses is repeated again from address 000.

Thus, the proposed device transmits eight 32-bit words to the line, the information part of each of which includes information from 16 sensors 13, totaling 128 sensors.

The number of inputs 128 is arbitrary, it can be significantly increased, while the structural scheme does not change, but the expansion of the size of its elements, namely, counter 27, decoder 14, matching elements 5 and selector 1 pulses, will be required.

Thus, the proposed device has greater reliability of the transmitted information, since the address code 0 of the transmitted word enters the decoder and uniquely identifies the group of sensors being polled, as well as a greater level of protection against interference, due to the use of matching elements, the installation of each pulse selector at the output of a sequential two-polar code with the introduction of parity into it.

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Claims (1)

Invention Formula 0 Device for information input, containing the first multiplexer, three triggers, pulse generator, the first element is NOT, the first counter, characterized in that, in order to increase the reliability of the entered information, matching elements are introduced into it, the second and third multiplexers, the counting trigger , decoder, second, third and fourth counters, seven elements OR NOT, two elements AND-NOT, second and third elements NOT, pulse selectors for duration, the inputs of which are device inputs, the outputs of which are connected to information the inputs of the first multiplexer, the output of which through the corresponding matching element is connected to the first input of the first, element with OR NOT, the output of the pulse generator is connected to the input of the first element NOT and the first inputs of the first and second elements NAND, the output of the first element is NOT connected to the counting inputs of the first, third and fourth counters, the outputs 0 group of the first counter and the outputs of the decoder through the corresponding matching elements connected to the address inputs of the first multiplexer, the output of the first counter connected to the blocking input of the second counter and the first input of the second element OR NOT, the outputs of the group of the second counter connected to the information inputs of the first group of the second multiplexer, output the second counter is connected to the reset input of the second counter; the output of the first counter and the outputs of the second counter group are connected to the inputs of the decryptor; the output of the second element nta OR-NOT connected to the synchronization inputs of the first and second triggers, the input of the second element is NOT, the output of which is connected to the input 5 resetting the third counter, the outputs of the group of which are connected to the address inputs of the second multiplexer, one of the outputs of the group of the third counter is connected to the first input5 0 the house of the third element OR NOT; the output of the third counter is connected to the second input of the second element OR NOT; the output of the fourth counter is connected to the installation inputs of the second and third triggers; the direct output of the first trigger is connected to the blocking input of the first counter and the first input of the fourth element OR- NOT, the output of which is connected to the input of the third element NOT and the blocking input of the third counter, the inverse output of the first trigger connected to the information inputs of the first and second triggers, the reset input of the first counter, the even input of the second counter and the second input of the first element OR NOT, the output of which is connected to the first input of the fifth element OR NOT, the second input of which is connected to the output of the OR element NO, the third input of the fifth element OR NOT connected to the third output the element OR NOT, the output is ten 15 the third element is NOT connected to the control input of the second multiplexer and the first input of the sixth element ORI, the second input of which is connected to the output of the second multiplexer, the information inputs of the second group of which are connected to the zero potential terminal, the information input to the output of the seventh element OR NOT the first input of which is connected to the direct output of the counting trigger, the synchronization input of the counting trigger is connected to the output of the first NAND element, the direct output of the third trigger is connected to the reset input of the fourth account ik and the second input of the second element AND - NOT, the inverse output of the third trigger is connected to the reset input of the counting trigger, the blocking input of the fourth counter and the second input of the fourth element OR-- NOT, the first and second information inputs of the third multiplexer are connected to the | NOT connected to the second positive potential, the third and the fourth one of the first NAND and the first address input of the third multiplexer, whose outputs are the device outputs, the second address input of the third multiplexer connected to the output of the second AND-NO element, a direct output of the second flip-flop is connected to the input of the third flip-flop and the second inputs of synchronization of the third and seventh OR-NO elements, an inverse output of the second flip-flop is connected to the reset input of the first flip-flop output The third information multiplexer inputs are connected to the negative potential bus, the fifth, sixth, seventh and eighth information inputs and the control input of the third multiplexer are 25 potential zero, the reset inputs of the second and third triggers, the installation inputs of the first and counting triggers and the information input of the third trigger is connected with a zero potential. ten 15 eight the third element is NOT connected to the control input of the second multiplexer and the first input of the sixth element ORI, the second input of which is connected to the output of the second multiplexer, the information inputs of the second group of which are connected to the zero potential terminal, the information input to the output of the seventh element OR NOT the first input of which is connected to the direct output of the counting trigger, the synchronization input of the counting trigger is connected to the output of the first NAND element, the direct output of the third trigger is connected to the reset input of the fourth account ik and the second input of the second element AND - NOT, the inverse output of the third trigger is connected to the reset input of the counting trigger, the blocking input of the fourth counter and the second input of the fourth element OR-- NOT, the first and second information inputs of the third multiplexer are connected to , the third and fourth information inputs of the third multiplexer are connected to the negative potential bus, the fifth, sixth, seventh and eighth information inputs and the control input of the third multiplexer are connected to 5 with zero potential, the inputs of the second and third trigger drops, the installation inputs of the first and counting triggers and the information input of the third trigger are connected with the zero potential.