SU1385310A1 - Synchronization device - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to simplify the device. The device contains r-1 pulses, a block 2 delays, el-i 3 and 4, an inverter 5. el-OR OR 6. pulse counters (SI) 7 and 8, triggers (T) 9 and 10. T 9 made as an RS flip-flop. To achieve the goal, T 1.0 is designed as a D-flip-flop. The output of the I-4 and 4 is connected to the D-input of T 1.0, the C-input of which is combined with the counting input of the SI 8. The output of Mr. I is connected to the 1st input of the E-4 and 4. In the initial state of the SI 7 and 8, T 9l 10 are in the zero state. El-t 3 is closed. Upon receipt of information. "I el-t I 4 opens for the passage of pulses from mr. 1 to the D-input T 10 and to the 2nd input of the el-OR 6. From the output of el-6, they go to the counting input of SI 7 and to S - The input of T 9, to-ry switches to the state; 1st "1, opening the elec I 4 and allowing the operation of the SI 8. When receiving the K-bit information. words to the counting input of the SI 8 receive the K th pulse from the output of the SI 7. At the output of the SI 8 there appears a pulse, which arrives at the R input T 9 and sets it to the zero state, closing the el 3 and resetting SI 8. The device returns to its original state. Block 2 ensures that the building pulses hit the middle of the information. pulses. 2 Il. & (L

Description

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The invention relates to telecommunications and can be used in discrete information transmission systems.

The aim of the invention is to simplify the device.

FIG. I represents the structural electrical circuit of the proposed synchronization device; in fig. 2 - timing diagrams explaining the operation of the synchronization device.

The synchronization device contains a generator of 1 pulses, a block 2 of delay, the first and second elements AND 3 and 4, the inverter 5, the element OR 6, the first and second counters 7 and 8 of the pulses, the first 9 and second Yu triggers.

The synchronization device operates as follows.

In the initial state, the first and second counters 7 and 8, the RS flip-flop 9 and the second flip-flop 10 (Fig. 1) are in the zero state. The first element And 3 is closed.

If the information sync (Fig. 2 a) receives the information "1 (each K-bit information word starts with the information" 1), the second element I 4 is opened for passing the pulses from the output of the generator 1 (Fig. 2 b) to the WR input of the second trigger 10 and to the second input of the YL-I element 6 (Fig. 2c). From the output of the element OR 6 they arrive (Fig. 2e) at the counting input of the first counter 7 and on the S input of iiepnoro trigger 9, which switches to the state "1 (Fig. 2g), thereby opening the AND 4 element (for passing the pulses of the generator 1 at the moments of the arrival at the device input of the information "O) and allowing the operation of the second counter 8.

After the t-th pulse of the generator 1, for example, the furnace of the 4th (Fig. 2) at the output of the first counter 7 appears a pulse (Fig. 2 g), which enters the C input of the second filter 10, setting it to “1 (Fig. 2 h), which corresponds to the appearance of“ 1 at the information output of the sync device. At the same time, a pulse from the output of the first counter 7 is fed to the counting input of the second counter B and to the input of the delay unit 2, from the output of which, after a time delay, appears at the gate output of the synchronization device as a gate (Fig. 2 and).

Upon receipt at the input of the synchronization device information "About the output of the second element And 4" About (Fig. 2 c) the operation of the synchronization device pass

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dit aggalogically described, only and 1puls of generator 1 passes through the first element AND 3 opened in this Case (Fig. 2 d) to the first input of the OR 6 element, and then to the counting input of the first counter 7 (Fig. 2 e) .

When the synchronization device receives the K-bit of the second Information word, the K-th pulse from the output of the first counter 7 (Fig. 2 g) enters the counting input of the second counter 8, resulting in the output O of the second. counter 8, a pulse (Fig. 2k) appears, which enters the R input of the first trigger 9 and sets it to the zero state (Fig. 2g), closing the first And 3 element and resetting the second counter, 5 hours. i.e. returns the synchronization device to its original state.

The delay unit 2 ensures that the strobe pulses fall into the middle of the information pulses (Fig. 2 h, i).

Claims (1)

Invention Formula A synchronization device1Ц1и containing a series-connected inverter, the first element AND, the element OR and the first pulse counter, serially connected the second pulse counter, and the first trigger, the direct output of which is connected to the second input of the first element AND and the enable input of the second pulse counter, as well as pulse generator, the second element And, the second trigger and the delay unit, the input of which is connected to the counting input of the second pulse counter, the first and second inputs of the second element And are connected respectively about to the third entrance of the first And element and the inverter input, the output of the second element AND is connected to the second input of the OR element, the output of which is connected to the S input of the first trigger, the first trigger being designed as the RS trigger, and the second input of the second element AND, the output of the delay block and the second output The flip-flop is, respectively, an input, gateway and informational output of the device, characterized in that, in order to simplify the device, the second trigger is designed as a D-flip-flop, while the output of the first element I is connected to the D-input of the second trigger, the C-input of which is combined with the counting input of the second pulse counter and connected to the output of the first pulse counter, and the output of the pulse generator is connected to the first input the second element I. FIG. g