SU1363303A1 - Memory with correcting errors - Google Patents

Abstract

The invention relates to computing and can be used in the design of storage devices. The aim of the invention is to increase the reliability of the device. The device contains a drive. input 1 and output 20 number registers;; address 3 register, coding block 5, correction block, control block 24, sampling decoder 10, address formers 49, first 6 and second 9 groups of elements AND, group 8 elements OR, element 12 In the device, the drive is divided into memory blocks, in each of which words are stored that have the same value of the control bits used as the leading bits of the address code. This eliminates the need for storing check bits in the accumulator, which leads to an increase in the reliability of the entire storage device, 2 sludge. i (L co 00 co o co

Description

eleven

The invention relates to computing and can be used in the design of storage device.

The aim of the invention is to increase the reliability of the device.

Figo is a diagram of the storage device with the correction opshbok | FIG 2 is a control block diagram.

The device (FIG.) Contains an input register 1 of a number with information inputs 2, a register of 3 addresses, with information inputs 4, a coding block 5, the first group of elements

And 6 with outputs 7 j group of elements OR 85 second group of elements AND 9, decoder 0 samples, blocks M pa30

mi, elements And 12, counters 13, de- 20 control in input register 1 s encoder 14, elements And 15, inputs 16, outputs 17 and 18, block 19 correction, register output 20 numbers with outputs 21, element And 22 s output 23, control block 24 with inputs 25-27 and outputs 28-35,

The control unit 24 (FIG. 2) contains the shift register 36, the generator 37, the element AND the 38 elements OR 39- ,,: 41, the elements AND 42 - 48,

Blocks 12 to 15 in FIG. 1 are combined into address formers 49.

It is assumed that for detecting and correcting errors of the i-th multiplicity it is necessary to form R check bits o Then the number of memory blocks 11 and, therefore, elements of AND 12, counters 13, decoders 14, elements of AND 15 is chosen equal. that in each memory block skid mc

35

Input 2 is received recorded from the wave. It is fed to coding unit 5, where the necessary check bits are formed to ensure 25 detection and correction of errors i of multiplicity. In addition, the recorded word is fed to the information inputs of the memory blocks 11 for the purpose of the next recording.

The signal from the output 30 controls the control bits through the first group of cells And 6 to one of the inputs of the SHSh 8 elements and then to the descriptor 10. The control bits of the hearth also go to the output 7 of the device and use them later as older ones Address addresses are written to the word. At the output of the decoder 10, a signal is generated to access one of the memory blocks 11 in accordance with the received kodo. Thus, the check bits ensure the selection of a specific memory block are the highest address bits.

40

words having the same combination of check bits; (control code).

The memory device with the error correction works as follows:

First, in the recording mode, the information is entered in the device memory 11 blocks. About this mode, a signal is received at the device input 26 that determines the recording mode, and at input 27 the initial setting signal C of the input 26 signal goes to the control unit 24 and to the control input inputs of the memory block 11. The signal from input 27 goes to the reset inputs of counters 13 and to control unit 24 where sets the first trigger of shift register 36 to unit state j and the other register triggers to zero. Signal from input 26 through element OR 39 opens element 38 and clock signals from generator 37, through element 38, arrive at the shift input of register 36. The unit recorded in the first trigger shifts in each clock signal to the next register bit. The signals from the unit outputs of the triggers of register 36 are sent to the elements OR 40 and 41 and the elements AND 42 - 48 o At the outputs of the elements 43, 44, 46 and 48, control signals are generated that ensure the device operates in the recording mode

The signal from the output of 28 block 24

0

0 control to input register 1 s

five

the input 2 is taken the recorded word o It goes to coding unit 5, where the necessary check bits are formed to ensure the 5th error detection and correction of the i-th multiplicity. In addition, the recorded word is fed to the information inputs of the memory blocks 11 for subsequent recording.

The signal from output 30 controls the bits through the first group of elements And 6 to one of the inputs of the elements SH 8 and then to the decoder 10. The control bits are also fed to output 7 of the device and are used later as high bits of the address to written word. At the output of the decoder 10, a signal is generated to access one of the memory blocks 11 in accordance with the received codeo. Thus, the check bits provide for the selection of a specific memory block and are the high-order address bits.

The signal at the output 33 of the control unit 24 starts the selected memory unit 11. The address of the memory unit cell is determined by the corresponding decoder 14, the input of which receives signals from the output of the corresponding counter 13, the signals from the outputs of the counter 13 are also fed to the output 17 of the device for the purpose of subsequent use for forming the readout address about. Since all the counters 13 are previously zeroed out, the word is written into the zero cell of the selected accumulator. At the same time, the signal is interrogated by the signal 34

0

five

five

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counters 13. If all the units are recorded in the counter, i.e. its content is maximal, then from the last (senior) output of the corresponding decoder 14, the signal through the element 15 arrives at the output 18 of the device. This signal is an indication that all the cells in a given memory block are full and long. further recording is necessary to increase its capacity.

The signal from output 32 through the corresponding element And 12, open sig

The output from the decoder 10, the second group, 15, and the elements of 8, 8, download the addition of the unit to the corresponding counter 23 and, that caiejM, forms the address of the next cell for the given memory block.

At this cycle, the recording of the word ends and the next spova is recorded. If a recording is made in the same memory block, the word is entered into the next cell. If it is written to another memory block, then it starts from zero. Under the influence of the shift signals, the unit circulates in the ring in the shift register 36, ensuring the formation of the necessary control signals. The end of the recording process is determined by the removal from input 26 of the control signal device.

- At the end of the recording of information in each block of 11 memory, words are written, having the same test bits.

The read mode is determined by the signal input to the device input 25, and the initial setting signal at input 27. The initial installation signal zeroes the counter 13 and initializes the triggers of the shift register 36 of the control unit 24. The signal from input 25 is fed to memory blocks 11 and determines their mode of operation. In control block 24, this signal opens element 38 through element RSHI 39, and element 38 arrives at register 36, output 42 of elements 45, 45 and 47 signals are generated that are controlled by the interaction of the device blocks in the read mode about

The signal from output 29 to register 3 from input 4 receives address bits that determine the number of memory block 11. These bits are in fact the control code for the word to be read. The signal from output 29 also goes to the control inputs of counters 13 and receives from them the input of 16 low-order bits of the address, which determine the number 1 of the cell to be addressed. Decoders 14 prepare the choice of the cell in accordance with the adress: SOMO

The signal from the output 31 of the block 24 control higher bits of the address I of the register 3 through the elements 9

0

five

0

five

0

five

0

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blunt to the decoder 10 to select one of the drives.

On a signal from the output 33 of the control unit 24, the selected memory unit 11 is launched, and the contents of the cell defined by the decoder 14 are read into the correction unit 19. Block 19, in addition, comes from the output of the AND 9 elements of the higher address bits, which are the control bits in the correction block 19, the realization) is the detection and, if possible, error correction.

The signal from output 35 takes the corrected word to output register 20 and then to output 21 If an unrecoverable error occurs in the read word, then the same signal at the output of the AND 22 element produces a signal that arrives at the output 23 of the device. The signal at this output indicates that the word in output register 20 contains uncorrectable errors.

Similarly, read the next word,

The end of the read mode is determined by the signal being removed from the input 25 of the device

Claims (1)

Invention Formula A memory device with error correction containing memory blocks whose information inputs are connected to the inputs of a coding block and to the outputs of an input number register whose information inputs are information inputs of a device, and a synchronous input connected to the first output gate of the control unit, the second and third outputs gating of which is connected respectively to the synchronous inputs of the address register and the output number register, whose outputs are informational outputs of the device, and informational inputs are connected to informational outputs of a correction unit, whose information bits are connected to the outputs of memory blocks, and the control bits connected to the outputs of the elements of the second group and to the second inputs of the elements OR of the group, the first inputs of which are connected to the outputs of elements AND of the first group, the first inputs of which are connected The yucheny to the outputs of the coding unit, and the second inputs are connected to the output of the record attribute of the control unit, the output of the read attribute of which is connected to the second inputs of the elements of the second group, the first inputs of which are connected to the outputs of the address register, the information inputs of which are the inputs of the higher address bits The devices, the inputs of the signs of writing and reading of the control unit are connected to the like inputs of the memory blocks and are the write and read inputs of the device, the input of the initial installation of the control unit is the same an input device, handling of the control unit output is connected with the same inputs of the memory blocks vyhodyoelemen comrade OR connected to inputs 33 W deshifraJ5 L-l-1-4r and. 5 0 0 5 five The sample torches, the outputs of which are connected to the sample inputs of the corresponding memory blocks, the outputs of the elements of the first group are the outputs of the higher address bits of the device, due to the fact that, in order to increase reliability, address drivers by the number of blocks are entered into the device. the memory and the And element, and the inputs of the And element are connected to the output of the error sign of the correction unit and to the third output of the gating of the control unit, the fourth and second outputs of the gating of which are connected respectively to the first and second sync The address shaper inputs whose address inputs are the low-order device address slots, the output of the address incrementing attribute of the control unit is connected to the address shaper inputs whose sample inputs are connected to the corresponding outputs of the sample decoder, the initial settings of the address shapers are connected to the same name to the device input, the address outputs of the address formers are connected to the address inputs of the corresponding memory blocks, the outputs of the overflow indication form ers addresses are homonymous outlets device, and the output member and is the output of the error flag, ge 2i t, P l to s Editor L. Veselovska Tehred L. Oliynyk Order 6369/45 Circulation 588 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab. D. 4/5 Production and printing company, Uzhgorod, ul, Proektna, 4 Corrector AoZimokosov