SU1539844A1 - Direct-access storage with error correction - Google Patents

Abstract

The invention relates to computing and can be used in main storage devices of digital computers. The purpose of the invention is to increase the reliability of storage devices. The device contains matrix drives 1 ₁ - 1 _N , column decoders 2 ₁ - 2 _N and rows 3 ₁ - 3 _N , address transformers of columns 4 ₁ - 4 _N and rows 5 ₁ -5 _N , address registers of columns 6 and rows 7, register 8 data, encoder 9, first 10 and second 11 decoders of matrix array number, double error detection unit 12, elements AND 13 ₁ - 13 _N , elements 14 ₁ - 14 _N , adders 15 ₁ - 15 _N modulo two, block 16 decoding and detection of a one-time error. In the device, the matrix accumulator defects are randomly distributed using converters 4 and 5 to "concentrate"("assemble") in the area of drives 1, different (by addresses) for individual drives. 1 il.

Description

The invention relates to computing and can be used in the main storage devices of digital EPM.

The purpose of the invention is to increase the reliability of the device.

The drawing shows a block diagram of a random access memory with error correction.

Random access memory (RAM) with error correction contains n matrix drives 1, -1n, n decoders 2, -2p columns and n decoders 3 (-3P lines, n converters 4, - 4 column addresses, n converters 5 (- 5p row addresses. The address of the memory location to be accessed (for writing or reading) is divided into a column address and a row address, which are respectively placed in the column address register 6 and the row address register 7. Recorded information enters the register 8 data k bits, (n k) - integer, the output of which is It contains the first 10 and second 11 decoders of the matrix storage number, a double error detection unit 12, n elements OR, n elements And n adders 15, - 15p modulo two, decoding unit 16 and detecting a one-time error.

RAM works as follows. Accumulators 1, 1P may contain defective columns, rows and individual cells, the location of which is

is determined by technological testing or storage testing by the operating system. Converters and 5, -5n are, for example, storage devices, the address inputs of which receive the column and row addresses, respectively, and the contents of the cells are the actual number of the used column or drive row. If technological testing of drives is performed, then address converters can be permanent storage devices programmed during device manufacturing. When testing by the operating system, RAM can be used as converters.

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We are able to test (blocks and communications necessary for entering information into address converters are not fundamental for the operation of the proposed device and are not shown in the drawing).

The principle of converting the addresses of columns and rows is as follows. The numbers of defective columns (rows) of the 1st accumulator (1 i. P) are stored in the memory of the 1st converter of the address of columns (rows) in the input address area (i-1) L, .o., IL, where L - the nearest is a power of two, greater than M / k; M is the number of columns (rows) of the accumulator. The additional memory cells corresponding to the remaining input addresses are filled with non-defective columns (rows). The maximum allowable number of defective columns (rows) of the main drive L, i.e. with n 7 and m 512, 64 defective columns (rows) are permissible.

In such a case, the defective columns (rows) of the 1st accumulator are concentrated in the area of the input addresses of the columns (rows) (i-1) L, ..., i-L and are not used at the same time in more than one accumulator. This achieves the fact that in the word read from the accumulator, in the worst case there are two errors (if the address of the column is in the defective area and the row address in the defective area of the other accumulator). Decoders 10 and 11 are used to indicate word bits — numbers of drives in which errors may occur when reading. These decoders have n outputs and are controlled by the high bits of register 7 and register 6, respectively.

At the output of the element OR 13, 1 is generated, which indicates the possibility of an error in the ith category (it should be noted that the presence of a unit does not necessarily indicate the presence of an error).

From the output of accumulator 1, the p-bit word is fed to the input of block 12, which can be represented by a decoder circuit of the Hamming code in the error detection mode. At the output of block 12, in the event of errors, signal 1 is generated. This signal goes to one of the inputs of elements AND 14, At the outputs of elements AND 14 in bits that contain a defective row and a defective column, a signal 1 is generated, which is fed to the input

modulo adder 15 modulo two. In case of detection of errors, a signal inverted to the signal of accumulator 1 appears at the output of the corresponding adder T5 modulo two. Thus, a code combination containing no more than one error arrives at the input of block 16. After decoding and correcting single errors in block 16, information is output to the device

The defects of the individual storage elements of the decoders of the columns and rows in the device can be identified with the defect of the column or row and eliminated in a similar way. The device corrects random failures caused, for example, by the discharge of the capacitors of the dynamic memory matrices when exposed to alpha particles, if they do not cause double errors.

A significant part of the defects of the additional storage devices in the address and column address conversion blocks can be eliminated by appropriate programming. So, if the memory of the column address transformer is made as a set of nine accumulators (32 columns by 16 rows; 512 columns of the main accumulator) and contains a defective column in one of the bits, only 16 of the 512 input addresses of the column are converted with an error . If, for example, a defect is caused by a bus bar closing onto the device case, O is read in the defective bit, regardless of the information being written. As one of the bits is uncontrollable, the defective addresses of the additional storage device allow only half of the main drive columns to be addressed. If this defect is revealed during testing, then it is not an obstacle to the normal operation of the device. To correct it, sufficiently remaining columns of the main storage device should be distributed between serviceable addresses of the additional storage device. Similarly, bus closures to the power source, bus closures, bus interruptions, etc. can be corrected.

It should be noted that the speed of the proposed device in terms of. depends on the speed of the address and column address converters. As the latter, it is advisable to use storage devices with a short sampling time. So, when implementing a large-capacity dynamic storage device in an additional storage device, it is advisable to use static storage elements.

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Claims (1)

Invention Formula Random access memory with error correction, containing n matrix drives (where n is the size of stored numbers), n column decoders, n row decoders, encoder, single error decoding and correction unit and double error detection unit, with outputs of 1 column decoder and strings 5 (, p) are connected to the corresponding sample inputs of the 1st matrix accumulator, the outputs of the matrix accumulators are connected to the corresponding inputs of the double error detection unit, the information inputs of the matrix accumulators are connected to the corresponding outputs of the encoder, the inputs of which are information inputs of the device are the outputs of the decoder unit and the correction of a one-time error, characterized in that, in order to increase the reliability of the device, n converters are inserted into it row addresses, n converters column addresses, n elements AND, n OR elements, n modulo two-, first and second decoders matrix matrix numbers, the outputs of each row address converter are connected to the inputs of the corresponding row decoder, the outputs of each column address converter are connected with the inputs of the corresponding column decoder, the inputs of the address and column address converters are respectively the first and second groups of device address inputs, the inputs of the first and second descript Ator room accumulator matrix are respectively connected to the inputs of high bits of the first and second groups of address input devices, outputs, a first decoder five 0 five 0 five matrix accumulator numbers are connected to the first inputs of the OR elements, the second inputs of which are connected to the outputs of the second decoder matrix matrix storage numbers, outputs of the OR elements are connected to the first inputs of the corresponding AND elements, the second inputs of which are connected to the output 1 of the double error detection unit The output of each element I is connected to the first input of the corresponding modulo two adder, the second input of which is connected to the output of the corresponding matrix accumulator, and the outputs of the modulo two adders are connected to the corresponding inputs of the decoding unit and the one-time error correction.