JP4241580B2 - Serial access memory - Google Patents

Description

  The present invention relates to a serial access memory and a data write / read method for the serial access memory.

  According to the line access type serial access memory, when a line address (X address) is given from the outside, an access (write / read operation) to a word line specified by the line address is performed. The configuration of a conventional line access type serial access memory 1 is shown in FIG.

  A conventional serial access memory 1 includes a memory cell array 11, a memory control unit 12, an X address means 13, a write Y address means 14, a read Y address means 15, a write side first transfer means group 16, a write register group 17, and a write side. A second transfer means group 18, a read side first transfer means group 19, a read register group 20, a read side second transfer means group 21, an input means 22, and an output means 23 are provided.

  The X address means 13 is controlled by the memory control unit 12 to select one word line from a plurality of word lines WL1 to WLn (n is a positive integer) and set it to a logical high level (H level).

  The memory cell array 11 includes a plurality of memory cells MC11 to MCmn arranged at intersections of a plurality of word lines WL1 to WLn and a plurality of bit line pairs BL1, / BL1 to BLm, / BLm (m is a positive integer). It is configured. Each memory cell MC11-MCmn includes one transistor (not shown) and one capacitor (not shown).

  Sense amplifiers SA1 to SAm are connected to the bit line pairs BL1, / BL1 to BLm, / BLm, and potential changes appearing in the bit line pairs BL1, / BL1 to BLm, / BLm by these sense amplifiers SA1 to SAm. Is amplified.

  Next, the circuit configuration on the write side as viewed from the memory cell array 11 will be described.

  The bit line pairs BL1, / BL1 to BLm, / BLm are connected to the write register group 17 via the write side first transfer means group 16. The write side first transfer means group 16 is composed of write side first transfer means 16-1 to 16-m corresponding to the bit line pairs BL1, / BL1 to BLm, / BLm. The write register group 17 includes write registers Wreg-1 to Wreg-m corresponding to the bit line pairs BL1, / BL1 to BLm, / BLm.

  Each write side first transfer means 16-1 to 16-m is composed of two transistors. For example, the bit line BL1 is connected to the write register via the drain / source of one transistor constituting the write side first transfer means 16-1, and the bit line / BL1 is connected to the write register via the drain / source of the other transistor. Connected to Wreg-1. The 2 · m transistors constituting the write side first transfer means 16-1 to 16-m are ON / OFF controlled by the control signal WT.

  The write register group 17 is connected to the write data buses WD and / WD via the write side second transfer means group 18. The write side second transfer means group 18 is composed of write side second transfer means 18-1 to 18-m corresponding to the write registers Wreg-1 to Wreg-m constituting the write register group 17, respectively.

  Each write side second transfer means 18-1 to 18-m is composed of two transistors. For example, the write register Wreg-1 is connected to the write data buses WD and / WD via the drain and source of two transistors constituting the write side second transfer means 18-1. The write Y address signals YW1 to YWm output from the write Y address means 14 are inputted to the write side second transfer means 18-1 to 18-m, and the write side second transfer means 18-1 to 18-1 to 18-m. The two transistors constituting 18-m are on / off controlled by write Y address signals YW1 to YWm.

  The write data buses WD and / WD are connected to the input terminal DIN via the input means 22.

  Next, the circuit configuration on the read side as viewed from the memory cell array 11 will be described.

  The bit line pairs BL1, / BL1 to BLm, / BLm are connected to the read register group 20 via the read side first transfer means group 19. The read side first transfer means group 19 is composed of read side first transfer means 19-1 to 19-m corresponding to the bit line pairs BL1, / BL1 to BLm, / BLm. The read register group 20 includes read registers Rreg-1 to Rreg-m corresponding to the bit line pairs BL1, / BL1 to BLm, / BLm.

  Each of the read side first transfer means 19-1 to 19-m is composed of two transistors. For example, the bit line BL1 is connected to the read register via the drain / source of one transistor constituting the read side first transfer means 19-1, and the bit line / BL1 is connected to the read register via the drain / source of the other transistor. It is connected to Rreg-1. The 2 · m transistors constituting the read side first transfer means 19-1 to 19-m are on / off controlled by a control signal RT.

  The read register group 20 is connected to the read data buses RD and / RD via the read side second transfer means group 21. The read-side second transfer means group 21 is composed of read-side second transfer means 21-1 to 21 -m corresponding to the read registers Rreg-1 to Rreg-m constituting the read register group 20.

  Each of the read side second transfer means 21-1 to 21-m is composed of two transistors. For example, the read register Rreg-1 is connected to the read data buses RD and / RD via the drains and sources of two transistors constituting the read side second transfer means 21-1. Read Y address signals YR1 to YRm output from the read Y address means 15 are inputted to the respective read side second transfer means 21-1 to 21-m. The two transistors constituting 21-m are on / off controlled by read Y address signals YR1 to YRm.

  The read data buses RD and / RD are connected to the output terminal DOUT via the output means 23.

  The operation of the conventional serial access memory 1 configured as described above will be described with reference to FIGS.

  FIG. 12 is a timing chart showing the write operation of the serial access memory 1. Hereinafter, the write operation will be described for each time in the figure.

  <Time t1> The write operation is started when the write X address WXAD is serially input to the memory control unit 12. In order to capture the write X address WXAD into the memory control unit 12, an H level write address enable signal WADE is input to the memory control unit 12 in advance. First, at time t1, the most significant bit (MSB) data Am of the write X address WXAD is taken into the memory control unit 12. Thereafter, each bit data of the write X address WXAD is sequentially taken into the memory control unit 12 in synchronization with the clock signal CLK.

  <Time t2> The data A1 of the least significant bit (LSB) of the write X address WXAD is taken into the memory control unit 12, and the taking of the write X address WXAD is completed. Here, the write address enable signal WADE input to the memory control unit 12 is set to a logical low level (L level). Hereinafter, a description will be given in the case where the word line WL1 is selected by the write X address WXAD.

  <Time t3> The word line WL1 selected at time t2 is set to H level by the X address means 13, and the control signal WT is set to H level by the memory control unit 12. As a result, each data stored in the memory cells MC11 to MCm1 connected to the word line WL1 is simultaneously transmitted to the write registers Wreg-1 to Wreg-m via the write side first transfer means group 16. Forwarded to Then, according to the contents of the input data DI1 to DIm written in the memory cells MC11 to MCm1, some bits of the data transferred to the write registers Wreg-1 to Wreg-m are masked (write mask operation). . Thereby, the efficiency of the write operation of the input data DI1 to DIm to the memory cells MC11 to MCm1 is improved.

  <Time t4> At the rising timing of the clock signal CLK, the memory control unit 12 detects the H level write enable signal WE. Thereby, a substantial write operation is started. The write Y address means 14 selects the write Y address signal YW1 from the write Y address signals YW1 to YWm and sets it to the H level. At this time, the input data DI1 input from the input terminal DIN is transmitted to the write data buses WD and / WD via the input means 22. Since the write-side second transfer means 18-1 is turned on by the H level write Y address signal YW1, the input data DI1 is stored in the write register Wreg-1.

  <Time t4 to t5> From time t4 to time t5, the write Y address means 14 sequentially selects the write Y address signals YW2 to YWm from the write Y address signals YW1 to YWm in synchronization with the clock signal CLK. Set to H level. On the other hand, input data DI2 to DIm are sequentially input to the input terminal DIN, and each input data DI2 to DIm is stored in the write registers Wreg-2 to Wreg-m.

  <Time t6> The H level write reset signal WR is input to the memory control unit 12, and the transfer of the input data DI1 to DIm stored in the write register group 17 to the memory cell array 11 is started.

  <Time t7> The word line WL1 selected at time t1 to t2 is set to H level by the X address means 13, and the control signal WT is set to H level by the memory control unit 12. As a result, the input data DI1 to DIm stored in the write register group 17 are transferred simultaneously to the memory cells MC11 to MCm1 connected to the word line WL1.

  As described above, according to the conventional serial access memory 1 of the line access type, a write operation can be performed for each X address (here, the word line WL1).

  FIG. 13 is a timing chart showing the read operation of the serial access memory 1. Hereinafter, the read operation will be described for each time in the figure.

  <Time t1> The read operation is started when the read X address RXAD is serially input to the memory control unit 12. Note that an H level read address enable signal RADE is input to the memory control unit 12 in advance in order to capture the read X address RXAD into the memory control unit 12. First, at time t1, the most significant bit (MSB) data Am of the read X address RXAD is taken into the memory control unit 12. Thereafter, each bit data of the read X address RXAD is sequentially taken into the memory control unit 12 in synchronization with the clock signal CLK.

  <Time t2> The data A1 of the least significant bit (LSB) of the read X address RXAD is taken into the memory control unit 12, and the reading of the read X address RXAD is completed. Here, the read address enable signal RADE input to the memory control unit 12 is set to the L level. Hereinafter, a description will be given in the case where the word line WL1 is selected by the read X address RXAD.

  <Time t3> The word line WL1 selected at time t2 is set to the H level by the X address means 13, and the control signal RT is set to the H level by the memory control unit 12. As a result, each data stored in the memory cells MC11 to MCm1 connected to the word line WL1 is simultaneously transmitted to the read registers Rreg-1 to Rreg-m via the read first transfer means group 19. Forwarded to

  <Time t4> At the rising timing of the clock signal CLK, the memory control unit 12 detects the H level read enable signal RE. Thereby, a substantial read operation is started. The read Y address means 15 selects the read Y address signal YR1 from the read Y address signals YR1 to YRm and sets it to the H level. Since the second transfer means 21-1 on the read side is turned on by the H level read Y address signal YR1, the data stored in the read register Rreg-1 is transmitted to the read data buses RD, / RD. The data transmitted to the read data buses RD, / RD is output to the output terminal DOUT via the output means 23 as the output data DO1.

  <Time t4 to t5> From time t4 to time t5, the read Y address means 15 sequentially selects the read Y address signals YR2 to YRm from the read Y address signals YR1 to YRm in synchronization with the clock signal CLK. Set to H level. Accordingly, each data stored in the read registers Rreg-2 to Rreg-m is sequentially transmitted to the read data buses RD and / RD. Each data sequentially transmitted to the read data buses RD, / RD is output to the output terminal DOUT through the output means 23 as output data DO2 to DOm.

  As described above, according to the conventional serial access memory 1 of the line access type, a read operation can be performed for each X address (here, the word line WL1).

  By the way, at the time t3 of the write operation of the serial access memory 1 shown in FIG. 12, the word line WL1 is changed to the H level, and each data stored in the memory cells MC11 to MCm1 is transferred to the write registers Wreg-1 to Wreg-m. In order to transfer, a time of 200 to 300 ns (write data transfer time) is required. Further, at the time t3 of the read operation of the serial access memory 1 shown in FIG. 13, the word line WL1 is changed to the H level and the data stored in the memory cells MC11 to MCm1 are read registers Rreg-1 to Rreg-m. It takes 200 to 300 ns (read data transfer time) in order to transfer data.

In the line type serial access memory 1, since the read operation and the write operation are asynchronously executed, the write data transfer operation from the time t3 in the write operation and the read data transfer operation from the time t3 in the read operation are timed. It is necessary to consider the case of overlapping. In addition, the self-refresh operation may overlap. Therefore, as shown in FIGS. 12 and 13, in the write operation and read operation of the serial access memory 1, the wait time (time t3) in which a margin is added to the write data transfer time, the read data transfer time, and the self refresh time. To t4: about 1.5 · s) is set as the functional specification.

In addition, there are the following as prior art documents related to the present invention.
JP-A 64-76600 JP-A-6-5095

  As described above, in the conventional serial access memory 1, after one X address is fetched from the outside to the memory control unit 12, in order to start a substantial write / read operation, the wait time elapses. I had to wait.

  In the development process or the manufacturing process, after writing predetermined data to each memory cell of the serial access memory 1, the data is read to test whether the data has been stored correctly. In the case of the line access type serial access memory 1, the above-described wait time is generated for each access to each X address. Therefore, in the test of the serial access memory 1 in which the write / read operation is performed on all X addresses, this wait time is a factor that hinders the reduction of the test time.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a serial access memory and a data write / read method capable of shortening a test time.

A serial access memory according to the present invention includes a memory cell array having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells;
A first register for storing data stored in a plurality of memory cells connected to each word line;
A second register for storing data stored in a plurality of memory cells connected to each word line;
A data input terminal to which input data is input;
An input / output means connected to the data input terminal, connected to the first register via the first data bus, transfers input data to the first register, and receives data from the first register;
A data output terminal for outputting output data;
An output means connected to the data output terminal and connected to the second register via the second data bus for receiving data from the second register;
A third data bus connected between the input / output means and the output means for transferring data received by the input / output means to the output means;

  The output means of the present invention compares the data received from the second register with the data received from the input / output means.

  Further, the third data bus may be connected to an inverter having the input / output means side as an input and the output means side as an output.

  Further, it may further include X address means, write Y address means, and read Y address means connected to the memory cell array.

It may further have a write Y address means for testing connected to the memory cell array.

  According to the present invention, the test time of the serial access memory can be shortened. In addition, measurement of the data transfer margin is facilitated.

  Exemplary embodiments of a serial access memory and a data write / read method according to the present invention will be described below in detail with reference to the accompanying drawings. In the following description and the attached drawings, constituent elements having substantially the same function and configuration are denoted by the same reference numerals, and redundant description is omitted.

[First Embodiment] FIG. 1 shows the configuration of a serial access memory 101 according to a first embodiment of the present invention.

  The serial access memory 101 according to the present embodiment includes a memory cell array 11, a memory control unit 112, an X address means 13, a write Y address means 14, a read Y address means 15, a write side first transfer means group 16, a write register group. 17, a write side second transfer means group 18, a read side first transfer means group 19, a read register group 20, a read side second transfer means group 21, an input / output means 122, and an output means 123.

  That is, the serial access memory 101 is different from the conventional serial access memory 1 in that the memory control unit 12, the input unit 22, and the output unit 23 are replaced with the memory control unit 112, the input / output unit 122, and the output unit 123, respectively. Is configured.

  The X address means 13 is controlled by the memory control unit 112 to select one word line from a plurality of word lines WL1 to WLn (n is a positive integer) and set it to the H level.

  The memory cell array 11 includes a plurality of memory cells MC11 to MCmn arranged at intersections of a plurality of word lines WL1 to WLn and a plurality of bit line pairs BL1, / BL1 to BLm, / BLm (m is a positive integer). It is configured. Each memory cell MC11-MCmn includes one transistor (not shown) and one capacitor (not shown).

  Sense amplifiers SA1 to SAm are connected to the bit line pairs BL1, / BL1 to BLm, / BLm, and potential changes appearing on the bit line pairs BL1, / BL1 to BLm, / BLm by these sense amplifiers SA1 to SAm. Is amplified.

  Next, the circuit configuration on the write side as viewed from the memory cell array 11 will be described.

  The bit line pairs BL1, / BL1 to BLm, / BLm are connected to the write register group 17 via the write side first transfer means group 16. The write side first transfer means group 16 is composed of write side first transfer means 16-1 to 16-m corresponding to the bit line pairs BL1, / BL1 to BLm, / BLm. The write register group 17 includes write registers Wreg-1 to Wreg-m corresponding to the bit line pairs BL1, / BL1 to BLm, / BLm.

  Each write side first transfer means 16-1 to 16-m is composed of two transistors. For example, the bit line BL1 is connected to the write register via the drain / source of one transistor constituting the write side first transfer means 16-1, and the bit line / BL1 is connected to the write register via the drain / source of the other transistor. Connected to Wreg-1. The 2 · m transistors constituting the write side first transfer means 16-1 to 16-m are ON / OFF controlled by the control signal WT.

  The write register group 17 is connected to the write data buses WD and / WD via the write side second transfer means group 18. The write side second transfer means group 18 is composed of write side second transfer means 18-1 to 18-m corresponding to the write registers Wreg-1 to Wreg-m constituting the write register group 17, respectively.

  Each write side second transfer means 18-1 to 18-m is composed of two transistors. For example, the write register Wreg-1 is connected to the write data buses WD and / WD via the drain and source of two transistors constituting the write side second transfer means 18-1. The write Y address signals YW1 to YWm output from the write Y address means 14 are inputted to the write side second transfer means 18-1 to 18-m, and the write side second transfer means 18-1 to 18-1 to 18-m. The two transistors constituting 18-m are on / off controlled by write Y address signals YW1 to YWm.

  The write data buses WD and / WD are connected to the input terminal DIN via the input / output means 122.

  Next, the circuit configuration on the read side as viewed from the memory cell array 11 will be described.

  The bit line pairs BL1, / BL1 to BLm, / BLm are connected to the read register group 20 via the read side first transfer means group 19. The read side first transfer means group 19 is composed of read side first transfer means 19-1 to 19-m corresponding to the bit line pairs BL1, / BL1 to BLm, / BLm. The read register group 20 includes read registers Rreg-1 to Rreg-m corresponding to the bit line pairs BL1, / BL1 to BLm, / BLm.

  Each of the read side first transfer means 19-1 to 19-m is composed of two transistors. For example, the bit line BL1 is connected to the read register via the drain / source of one transistor constituting the read side first transfer means 19-1, and the bit line / BL1 is connected to the read register via the drain / source of the other transistor. It is connected to Rreg-1. The 2 · m transistors constituting the read side first transfer means 19-1 to 19-m are on / off controlled by a control signal RT.

  The read register group 20 is connected to the read data buses RD and / RD via the read side second transfer means group 21. The read-side second transfer means group 21 is composed of read-side second transfer means 21-1 to 21 -m corresponding to the read registers Rreg-1 to Rreg-m constituting the read register group 20.

  Each of the read side second transfer means 21-1 to 21-m is composed of two transistors. For example, the read register Rreg-1 is connected to the read data buses RD and / RD via the drains and sources of two transistors constituting the read side second transfer means 21-1. Read Y address signals YR1 to YRm output from the read Y address means 15 are inputted to the respective read side second transfer means 21-1 to 21-m. The two transistors constituting 21-m are on / off controlled by read Y address signals YR1 to YRm.

  The read data buses RD and / RD are connected to the output terminal DOUT via the output means 123.

  The input / output means 122 located on the write side and the output means 123 located on the read side are connected by the second read data buses RD2, / RD2.

  The operation of the serial access memory 101 according to this embodiment configured as described above will be described with reference to FIGS. The serial access memory 101 is configured for the purpose of shortening the test time. Therefore, here, a read operation and a write operation in a test for determining whether or not correct data has been read after reading predetermined data into the serial access memory 101 will be described.

  FIG. 2 is a timing chart showing a write operation (test write operation) during a test of the serial access memory 101. Hereinafter, the test write operation will be described for each time in the figure.

  <Time t1> When the test write operation is started, the test mode signal TM is input to the memory control unit 112. The test write operation is started when the write X address WXAD is serially input to the memory control unit 112. Note that in order to capture the write X address WXAD into the memory control unit 112, an H level write address enable signal WADE is input to the memory control unit 112 in advance. First, at time t1, the most significant bit (MSB) data Am of the write X address WXAD is taken into the memory control unit 112. Thereafter, each bit data of the write X address WXAD is sequentially taken into the memory control unit 112 in synchronization with the clock signal CLK.

  <Time t2> The data A1 of the least significant bit (LSB) of the write X address WXAD is captured by the memory control unit 112, and the capture of the write X address WXAD is completed. Here, the write address enable signal WADE input to the memory control unit 112 is set to the L level. In this test write operation, the word line WL1 is first selected by the write X address WXAD.

  <Time t3> In the write operation of the conventional serial access memory 1 shown in FIG. 12, the write mask operation is performed. However, since the memory cells MC11 to MCmn of the serial access memory 101 where the test write operation is performed are in an initial state in which no data is stored, it is not essential to perform the write mask operation. Therefore, the write mask operation is omitted here.

  <Time t4> At the rising timing of the clock signal CLK, the memory control unit 112 detects the H level write enable signal WE. Thereby, a substantial test write operation is started. The write Y address means 14 selects the write Y address signal YW1 from the write Y address signals YW1 to YWm and sets it to the H level. At this time, the input data DI1 input from the input terminal DIN is transmitted to the write data buses WD and / WD via the input / output means 122. Since the write-side second transfer means 18-1 is turned on by the H level write Y address signal YW1, the input data DI1 is stored in the write register Wreg-1.

  <Time t4 to t5> From time t4 to time t5, the write Y address means 14 sequentially selects the write Y address signals YW2 to YWm from the write Y address signals YW1 to YWm in synchronization with the clock signal CLK. Set to H level. On the other hand, input data DI2 to DIm are sequentially input to the input terminal DIN, and each input data DI2 to DIm is stored in the write registers Wreg-2 to Wreg-m.

  <Time t6> The H level write reset signal WR is input to the memory control unit 112, and the transfer of the input data DI1 to DIm stored in the write register group 17 to the memory cell array 11 is started.

  <Time t7> The word line WL1 selected at time t1 to t2 is set to H level by the X address means 13, and the control signal WT is set to H level by the memory control unit 112. As a result, the input data DI1 to DIm stored in the write register group 17 are transferred simultaneously to the memory cells MC11 to MCm1 connected to the word line WL1.

  <Time t8> Again, the H level write reset signal WR is input to the memory control unit 112, and the transfer of the input data DI1 to DIm stored in the write register group 17 to the memory cell array 11 is started. The

  <Time t9> The word line WL2 of the next address of the word line WL1 selected at times t1 to t2 is set to H level by the X address means 13, and the control signal WT is set to H level by the memory control unit 112. As a result, the input data DI1 to DIm stored in the write register group 17 are transferred simultaneously to the memory cells MC12 to MCm2 connected to the word line WL2.

  <Time t10 to t13> From time t10 to time t13, the substantially same operation as that from time t6 to time t9 is repeated while incrementing the X address one by one. At time t13, when the input data DI1 to DIm stored in the write register group 17 are transferred all at once to the memory cells MC1n to MCmn connected to the word line WLn, the write register group 17 Transfer of the input data DI1 to DIm to the memory cell array 11 is completed. By this transfer operation, the same input data DI1 to DIm are stored for all the word lines WL1 to WLn for all the memory cells MC11 to MCmn.

  As described above, according to the test write operation of the serial access memory 101 shown in FIG. 2, the write operation of the input data DI1 to DIm to the write register group 17 is executed only once, and then the input written to the write register group 17 Data DI1 to DIm are transferred to all memory cells MC11 to MCmn. Therefore, as compared with the conventional write operation in which the input data for each word line is written to the write register group 17, the time required to store data for all the memory cells MC11 to MCmn is greatly reduced.

  FIG. 3 is a timing chart showing a read operation (test read operation) during a test of the serial access memory 101 according to the present embodiment performed subsequent to the test write operation of FIG. Hereinafter, the test read operation will be described for each time in the figure.

  <Time t1> When the test read operation is started, the test mode signal TM is input to the memory control unit 112. The test read operation is started when the read X address RXAD is serially input to the memory control unit 112. Note that an H level read address enable signal RADE is input to the memory control unit 112 in advance in order to capture the read X address RXAD into the memory control unit 112. First, at time t1, the most significant bit (MSB) data Am of the read X address RXAD is taken into the memory control unit 112. Thereafter, each bit data of the read X address RXAD is sequentially taken into the memory control unit 112 in synchronization with the clock signal CLK.

  <Time t2> The data A1 of the least significant bit (LSB) of the read X address RXAD is taken into the memory control unit 112, and the reading of the read X address RXAD is completed. Here, the read address enable signal RADE input to the memory control unit 112 is set to the L level. In this test read operation, the word line WL1 is first selected by the read X address.

  <Time t3> The word line WL1 selected at time t2 is set to the H level by the X address means 13, and the control signal RT is set to the H level by the memory control unit 112. As a result, the data stored in the memory cells MC11 to MCm1 connected to the word line WL1 are transferred to the read registers Rreg-1 to Rreg-m all at once via the read side first transfer means group 19. Is done.

  <Time t4> After the data stored in the memory cells MC11 to MCm1 connected to the word line WL1 are transferred all at once to the read registers Rreg-1 to Rreg-m, at time t4, the word line by the X address means 13 WL2 is set to H level, and the control signal WT is set to H level. As a result, the data stored in the memory cells MC12 to MCm2 connected to the word line WL2 are transferred all at once to the write registers Wreg-1 to Wreg-m via the write side first transfer means group 16. As described above, the write registers Wreg-1 to Wreg-m are used as temporary storage means for data read from the memory cells MC12 to MCm2.

  <Time t5> At the rising timing of the clock signal CLK, the memory control unit 112 detects the read enable signal RE at the H level. As a result, a substantial test read operation is started.

  The read Y address means 15 selects the read Y address signal YR1 from the read Y address signals YR1 to YRm and sets it to the H level. Since the read-side second transfer means 21-1 is turned on by the H level read Y address signal YR1, the data stored in the read register Rreg-1 is output via the read data buses RD, / RD. 123.

  At the same timing, the write Y address means 14 selects the write Y address signal YW1 from the write Y address signals YW1 to YWm and sets it to the H level. Since the write side second transfer means 18-1 is turned on by the H level write Y address signal YW1, the data stored in the write register Wreg-1 is input / output via the write data buses WD, / WD. The signal is transmitted to the means 122 and further transmitted to the output means 123 via the second read data buses RD2 and / RD2.

  The output means 123 compares the data transmitted from the read data buses RD and / RD with the data transmitted from the second read data buses RD2 and / RD2, and determines a match / mismatch. The determination result is output to the output terminal DOUT as output data DO1c. The data comparison means provided in the output means 123 is constituted by, for example, an ExOR (exclusive OR) gate.

  <Time t5 to t6> From time t5 to time t6, the read Y address means 15 sequentially selects the read Y address signals YR2 to YRm from the read Y address signals YR1 to YRm in synchronization with the clock signal CLK. Set to H level. Accordingly, each data stored in the read registers Rreg-2 to Rreg-m is sequentially transmitted to the output means 123 via the read data buses RD and / RD. Similarly, the write Y address means 14 sequentially selects the write Y address signals YW2 to YWm from the write Y address signals YW1 to YWm in synchronization with the clock signal CLK and sets them to the H level. Accordingly, each data stored in the write registers Wreg-2 to Wreg-m sequentially passes through the write data buses WD, / WD, the input / output means 122, and the second read data buses RD2, / RD2. It is transmitted to the output means 123. The output means 123 sequentially compares the data transmitted from the read data buses RD and / RD and the data transmitted from the second read data buses RD2 and / RD2 to determine coincidence / mismatch. The determination result is output to the output terminal DOUT as output data DO2c, DO3c,..., DOmc.

  <After time t7> From time t2 to time t6, the storage data of the memory cells MC11 to MCm1 connected to the word line WL1 and the storage data of the memory cells MC12 to MCm2 connected to the word line WL2 are compared. . Similarly, after time t7, t8, two word lines from word line WL3 to word line WLn are taken as one set, and the stored data of the memory cells connected to each word line are compared one by one.

  As described above, according to the test read operation of the serial access memory 101 shown in FIG. 3, the data stored in each of the memory cells MC11 to MCmn is read in the test write operation shown in FIG. It is determined whether or not.

  According to the read operation of the conventional serial access memory 1, the data stored in the memory cells connected to each word line is transferred to the read register group 20 for each word line, so that all the memory cells MC11 to MCmn When reading stored data, a wait time corresponding to the number of word lines is consumed. In this regard, according to the test read operation of the serial access memory 101 according to the present embodiment, the data stored in the memory cells connected to one word line is stored in the read register group 20 as a set of two word lines. The data stored in the memory cell connected to the other word line is transferred to the write register group 17. Then, the data stored in the read register group 20 and the data stored in the write register group 17 are compared in the output means 123 bit by bit. Therefore, the wait time is halved compared with the read operation of the conventional serial access memory 1, and the time required for the read operation in the test is greatly reduced.

  As described above, according to the configuration of the serial access memory 101 and its test write / read operation according to the present embodiment, predetermined data is written to all the memory cells MC11 to MCmn in the conventional serial access memory 1, and all Compared with the write / read operation of reading stored data from the memory cells MC11 to MCmn, a significant time reduction is realized.

  Next, another embodiment of the serial access memory 101 and the test read operation according to the present embodiment will be described.

  In the test read operation of the serial access memory 101 according to the present embodiment, as shown in FIG. 3, after time t5, the read Y address means 15 sequentially selects the read Y address signals YR1 to YRm and sets them to the H level. At the same timing, the write Y address means 14 sequentially selects the write Y address signals YW1 to YWm and sets them to the H level. As a result, the data string stored in the read register group 20 and the data string stored in the write register group 17 are transmitted bit by bit to the output means 123, and the data comparison means provided in the output means 123 performs bit conversion. Compared every time.

  On the other hand, the sequential selection of the read Y address signals YR1 to YRm by the read Y address means 15 and the sequential selection of the write Y address signals YW1 to YWm by the write Y address means 14 may be performed alternately. According to this method, each data stored in the read registers Rreg-1 to Rreg-m and each data stored in the write registers Wreg-1 to Wreg-m are alternately transmitted to the output unit 123. It will be. Then, the output means 123 is provided with switch means, and the switch means alternately selects the data transmitted from the read data buses RD and / RD and the data transmitted from the second read data buses RD2 and / RD2, Output to the output terminal DOUT. According to this configuration and method, the output means 123 need not be provided with a data comparison circuit, and the output means 123 can be configured in a compact manner.

  Further, after the sequential selection of the read Y address signals YR1 to YRm by the read Y address means 15, the write Y address means 14 may sequentially select the write Y address signals YW1 to YWm. According to this method, after all the data stored in the read registers Rreg-1 to Rreg-m are transmitted to the output unit 123, the data stored in the write registers Wreg-1 to Wreg-m It is transmitted to the output means 123. Compared with the case where the sequential selection of the read Y address signals YR1 to YRm by the read Y address means 15 and the sequential selection of the write Y address signals YW1 to YWm by the write Y address means 14 are alternately performed, the read Y address means 15 and the write Y address means 15 The control of the Y address means 14 is facilitated, and the scale reduction is realized in both the hardware and software of the memory control unit 112 in charge of this control.

[Second Embodiment] FIG. 4 shows the configuration of a serial access memory 201 according to a second embodiment of the present invention.

  The serial access memory 201 according to the present embodiment is obtained by adding inverters 211 and 212 to the serial access memory 101 according to the first embodiment. The inverters 211 and 212 are provided between the second read data buses RD2 and / RD2 and the output means 123, and the logic level of the data output from the input / output means 122 to the second read data buses RD2 and / RD2 Is inverted and supplied to the output means 123. The serial access memory 201 is the same as the serial access memory 101 except for the inverters 211 and 212.

  The operation of the serial access memory 201 according to this embodiment configured as described above will be described with reference to FIG. The serial access memory 201 is configured for the purpose of shortening the test time. Therefore, here, a read operation and a write operation in a test in which predetermined data is written to the serial access memory 201 and then data is read to determine whether or not correct data has been read will be described.

  FIG. 5 is a timing chart showing the test write operation of the serial access memory 201. Hereinafter, the test write operation will be described for each time in the figure.

  <Time t1> When the test write operation is started, the test mode signal TM is input to the memory control unit 112. The test write operation is started when the write X address WXAD is serially input to the memory control unit 112. Note that in order to capture the write X address WXAD into the memory control unit 112, an H level write address enable signal WADE is input to the memory control unit 112 in advance. First, at time t1, the most significant bit (MSB) data Am of the write X address WXAD is taken into the memory control unit 112. Thereafter, each bit data of the write X address WXAD is sequentially taken into the memory control unit 112 in synchronization with the clock signal CLK.

  <Time t2> The data A1 of the least significant bit (LSB) of the write X address WXAD is captured by the memory control unit 112, and the capture of the write X address WXAD is completed. Here, the write address enable signal WADE input to the memory control unit 112 is set to the L level. In this test write operation, the word line WL1 is first selected by the write X address WXAD.

  <Time t3> In the write operation of the conventional serial access memory 1 shown in FIG. 12, the write mask operation is performed. However, since the memory cells MC11 to MCmn of the serial access memory 101 where the test write operation is performed are in an initial state in which no data is stored, it is not essential to perform the write mask operation. Therefore, the write mask operation is omitted here.

  <Time t4> At the rising timing of the clock signal CLK, the memory control unit 112 detects the H level write enable signal WE. Thereby, a substantial test write operation is started. The write Y address means 14 selects the write Y address signal YW1 from the write Y address signals YW1 to YWm and sets it to the H level. At this time, the input data DI1 input from the input terminal DIN is transmitted to the write data buses WD and / WD via the input / output means 122. Since the write-side second transfer means 18-1 is turned on by the H level write Y address signal YW1, the input data DI1 is stored in the write register Wreg-1.

  <Time t4 to t5> From time t4 to time t5, the write Y address means 14 sequentially selects the write Y address signals YW2 to YWm from the write Y address signals YW1 to YWm in synchronization with the clock signal CLK. Set to H level. On the other hand, input data DI2 to DIm are sequentially input to the input terminal DIN, and each input data DI2 to DIm is stored in the write registers Wreg-2 to Wreg-m.

  <Time t6> The H level write reset signal WR is input to the memory control unit 112, and the transfer of the input data DI1 to DIm stored in the write register group 17 to the memory cell array 11 is started.

  <Time t7> The word line WL1 selected at time t1 to t2 is set to H level by the X address means 13, and the control signal WT is set to H level by the memory control unit 112. As a result, the input data DI1 to DIm stored in the write register group 17 are transferred simultaneously to the memory cells MC11 to MCm1 connected to the word line WL1.

  <Time t8> After each data stored in the write registers Wreg-1 to Wreg-m is transferred to the memory cells MC11 to MCm1 connected to the word line WL1, the word line WL3 is X address means. 13 is set to H level, and the control signal WT is set to H level by the memory control unit 112. As a result, the same input data DI1 to DIm as the data transferred to the memory cells MC11 to MCm1 connected to the word line WL1 are simultaneously transmitted to the memory cells MC13 to MCm3 connected to the word line WL3. Transferred.

  <After time t8> After the input data DI1 to DIm are transferred to and stored in the memory cells MC13 to MCm3 connected to the word line WL3, the odd numbered word lines WL5, WL7,. The same input data DI1 to DIm are transferred to the connected memory cells MC15 to MCm5, MC17 to MCm7,. As described above, the same input data DI1 to DIm are written to the memory cells connected to the odd-numbered word lines.

  After the same input data DI1 to DIm are written to the memory cells connected to the odd-numbered word lines, the serial access memory 201 repeats the test write operation shown in FIG. Input data / DI1 to / DIm is stored in memory cells MC12 to MCm2, MC14 to MCm4, MC16 to MCm6,... Connected to the numbered word lines WL2, WL4, WL6,. The input data / DI1 to / DIm are obtained by inverting the logic levels of the input data DI1 to DIm, respectively. For example, when the input data DI1 is “0”, the input data / DI1 is “1”.

  As described above, according to the test write operation of the serial access memory 201 according to the present embodiment, each memory cell connected to one word line is stored in each memory cell connected to an adjacent word line. Data obtained by inverting the logic level of the stored data is stored.

  In this test write operation, after the storage operation of the input data DI1 to DIm and the input data / DI1 to / DIm for the write register group 17 is executed once each, the data transfer for all the word lines WL1 to WLn is performed. Done. Therefore, as compared with the write operation of the conventional serial access memory 1 that stores input data in the write register group 17 every time each word line is accessed, the time required for storing data in all the memory cells MC11 to MCmn is greatly increased. To shorten.

  The serial access memory 201 according to the present embodiment performs a test read operation following the test write operation shown in FIG.

  The test read operation of the serial access memory 201 is performed in the same manner as the test read operation of the serial access memory 101 according to the first embodiment shown in FIG. That is, as a set of two word lines, data stored in memory cells connected to one word line is transferred to the read register group 20, and data stored in memory cells connected to the other word line is written. Transferred to the register group 17. Then, the data string stored in the read register group 20 and the data string stored in the write register group 17 are compared by the output means 123 bit by bit.

  However, unlike the test write operation of the serial access memory 101 according to the first embodiment in which the same data string is stored for each word line, according to the test write operation of the serial access memory 201, odd-numbered words Memory cells MC11 to MCm1, MC13 to MCm3,... Connected to lines WL1, WL3,... Have memory cells MC12 to MC12 connected to even-numbered word lines WL2, WL4,. Data obtained by inverting the logic level of the stored data of MCm2, MC14 to MCm4,. For example, when the input data DI1 to DIm = “01010... 1” is stored in the memory cells MC11 to MCm1 connected to the word line WL1, the memory cells MC12 to MCm2 connected to the word line WL2 are stored. Stores input data / DI1 to / DIm = “10101... 0”. In the test read operation, the storage data “01010... 1” of the memory cells MC11 to MCm1 is transferred and stored in the read register group 20, and the storage data “10101... 0” of the memory cells MC12 to MCm2 is The data is transferred and stored in the write register group 17.

  The data string “01010... 1” stored in the read register group 20 is transmitted bit by bit to the output means 123 via the read data buses RD and / RD.

  On the other hand, the data string “10101... 0” stored in the write register group 17 is transmitted bit by bit to the input / output means 122 via the write data buses WD and / WD, and further to the second read data bus RD2. , / RD2, and inverters 211 and 212 to be transmitted to the output means 123. Since the data string “10101... 0” stored in the write register group 17 passes through the inverters 211 and 212 in the middle, the logic level is inverted here, and the data string “01010. 123 is input.

  The output means 123 compares the data transmitted from the read data buses RD and / RD with the data transmitted from the second read data buses RD2 and / RD2, and determines a match / mismatch. At this time, since the logic level of the data transmitted from the second read data buses RD2 and / RD2 is inverted by the inverters 211 and 212 in advance, the data comparison means provided in the output means 123 is the second read data. Data transmitted from the buses RD2 and / RD2 can be directly compared with data transmitted from the read data buses RD and / RD. The determination result is output to the output terminal DOUT as output data DO1c.

  For the word lines WL3 to WLn other than the word lines WL1 and WL2, two word lines are set as one set, and the data stored in the memory cells connected to each word line are compared one by one by the output means 123.

  As described above, according to the test read operation of the serial access memory 201, the data stored in each of the memory cells MC11 to MCmn is read out in the test write operation shown in FIG. 5, and it is determined whether or not the data is stored correctly. Is done.

  Moreover, the stored data of the memory cells connected to one word line are transferred to the read register group 20 and the stored data of the memory cells connected to the other word line are written as a set of two word lines. Transferred to the register group 17. Then, the data string stored in the read register group 20 and the data string stored in the write register group 17 are compared in the output unit 123 bit by bit. Therefore, the time required for the test read operation can be greatly reduced as compared with the read operation of the conventional serial access memory 1 which accesses each word line, transfers the stored data to the read register group 20 and reads the data to the outside.

  As described above, according to the configuration of the serial access memory 201 and the test write / read operation according to the present embodiment, predetermined data is written to all the memory cells MC11 to MCmn in the conventional serial access memory 1, and all Compared with the write / read operation of reading stored data from the memory cells MC11 to MCmn, a significant time reduction is realized.

  By the way, according to the configuration of the serial access memory 101 and the test write / read operation according to the first embodiment, the same data string is stored in units of word lines in the memory cells connected to the respective word lines. The In this case, in the test, for example, it is assumed that the storage data of the memory cells MC11 to MCm1 connected to the word line WL1 and the storage data of the memory cells MC12 to MCm2 connected to the word line WL2 match. However, it is impossible to determine whether or not the selection of the word lines WL1 and WL2 has been performed without error in the test write operation or the test read operation. In this regard, according to the configuration of the serial access memory 201 and the test write / read operation according to the present embodiment, a data string whose logic level is inverted is stored for each adjacent word line, and the data string is read out. Therefore, it is possible not only to determine whether or not data is normally stored in each memory cell but also to determine whether or not the word line is selected.

[Third Embodiment] FIG. 6 shows the configuration of a serial access memory 301 according to a third embodiment of the present invention.

  The serial access memory 301 according to this embodiment is obtained by adding a write-side third transfer means group 311 to the serial access memory 201 according to the second embodiment. This write side third transfer means group 311 is composed of write side third transfer means 311-1 to 311-m corresponding to the respective bit line pairs BL1, / BL1 to BLm, / BLm.

  Each write-side third transfer means 311-1 to 311-m is composed of two transistors. The 2 · m transistors constituting the write side third transfer means 311-1 to 311-m are ON / OFF controlled by the control signal WT2.

  The serial access memory 301 connects the bit line pairs BL1, / BL1 to BLm, / BLm and the write registers Wreg-1 to Wreg-m. In addition to the write side third transfer means 311-1 to 311-m, , Write-side first transfer means 16-1 to 16-m that are on / off controlled by a control signal WT. When data stored in the write register group 17 is transferred to the memory cell array 11 via the bit line pairs BL1, / BL1 to BLm, / BLm, either the control signal WT or the control signal WT2 is set to the H level. The

  Complementary data is stored in each of the write registers Wreg-1 to Wreg-m. This complementary data is transferred to the bit line pairs BL1, / BL1 to BLm, / BLm by either the write side first transfer means 16-1 to 16-m or the write side third transfer means 311-1 to 311-m. Transferred. However, among the complementary data stored in the write registers Wreg-1 to Wreg-m, when the data is transferred by the write side first transfer means 16-1 to 16-m, it is output to the bit lines BL1 to BLm. When the data is transferred by the write side third transfer means 311-1 to 311-m, it is output to the bit lines / BL1 to / BLm. On the contrary, the data output to the bit lines / BL1 to / BLm when transferred by the write side first transfer means 16-1 to 16-m is written by the write side third transfer means 311-1 to 311-m. When transferred, it is output to the bit lines BL1 to BLm. Specifically, for example, the write register Wreg-1 so that the data “0” is transferred to the bit line pair BL1 and the data “1” is transferred to the bit line / BL1 by the write side first transfer means 16-1. Is stored in the bit line pair BL1, / BL1 by the write side third transfer means 311-1, the data "1" is stored in the bit line BL. "Is output, and data" 0 "is output to the bit line / BL.

  The operation of the serial access memory 301 according to this embodiment configured as described above will be described. The serial access memory 301 is configured for the purpose of shortening the test time. Therefore, here, a read operation and a write operation in a test for determining whether or not correct data has been read after reading predetermined data into the serial access memory 301 will be described.

  FIG. 7 is a timing chart showing the test write operation of the serial access memory 301. Hereinafter, the test write operation will be described for each time in the figure.

  <Time t1> When the test write operation is started, the test mode signal TM is input to the memory control unit 112. The test write operation is started when the write X address WXAD is serially input to the memory control unit 112. Note that in order to capture the write X address WXAD into the memory control unit 112, an H level write address enable signal WADE is input to the memory control unit 112 in advance. First, at time t1, the most significant bit (MSB) data Am of the write X address WXAD is taken into the memory control unit 112. Thereafter, each bit data of the write X address WXAD is sequentially taken into the memory control unit 112 in synchronization with the clock signal CLK.

  <Time t2> The data A1 of the least significant bit (LSB) of the write X address WXAD is captured by the memory control unit 112, and the capture of the write X address WXAD is completed. Here, the write address enable signal WADE input to the memory control unit 112 is set to the L level. In this test write operation, the word line WL1 is first selected by the write X address WXAD.

  <Time t3> In the write operation of the conventional serial access memory 1 shown in FIG. 12, the write mask operation is performed. However, since the memory cells MC11 to MCmn of the serial access memory 101 where the test write operation is performed are in an initial state in which no data is stored, it is not essential to perform the write mask operation. Therefore, the write mask operation is omitted here.

  <Time t4> At the rising timing of the clock signal CLK, the memory control unit 112 detects the H level write enable signal WE. Thereby, a substantial test write operation is started. The write Y address means 14 selects the write Y address signal YW1 from the write Y address signals YW1 to YWm and sets it to the H level. At this time, the input data DI1 input from the input terminal DIN is transmitted to the write data buses WD and / WD via the input / output means 122. Since the write-side second transfer means 18-1 is turned on by the H level write Y address signal YW1, the input data DI1 is stored in the write register Wreg-1.

  <Time t4 to t5> From time t4 to time t5, the write Y address means 14 sequentially selects the write Y address signals YW2 to YWm from the write Y address signals YW1 to YWm in synchronization with the clock signal CLK. Set to H level. On the other hand, input data DI2 to DIm are sequentially input to the input terminal DIN, and each input data DI2 to DIm is stored in the write registers Wreg-2 to Wreg-m.

  <Time t6> The H level write reset signal WR is input to the memory control unit 112, and the transfer of the input data DI1 to DIm stored in the write register group 17 to the memory cell array 11 is started.

  <Time t7> The word line WL1 selected at time t1 to t2 is set to H level by the X address means 13, and the control signal WT is set to H level by the memory control unit 112. As a result, the input data DI1 to DIm stored in the write register group 17 pass through the write side first transfer means 16-1 to 16-m and the memory cells MC11 to MCm1 connected to the word line WL1. Are transferred all at once.

  <Time t8> Again, the H level write reset signal WR is input to the memory control unit 112, and the transfer of the input data DI1 to DIm stored in the write register group 17 to the memory cell array 11 is started. The

  <Time t9> The word line WL2 of the next address of the word line WL1 selected at times t1 to t2 is set to H level by the X address means 13, and the control signal WT2 is set to H level by the memory control unit 112. As a result, the input data DI1 to DIm stored in the write register group 17 are transferred to the memory cells MC12 to MCm2 connected to the word line WL2 via the write side third transfer means 311-1 to 311-m. Are transferred all at once. At this time, data in which the logic level is inverted with respect to the data stored in the memory cells MC11 to MCm1 is stored in the memory cells MC12 to MCm2.

  <Time t10 to t13> From time t10 to time t13, the substantially same operation as that from time t6 to time t9 is repeated while incrementing the X address one by one. However, when data is transferred to the memory cells MC11 to MCm1, MC13 to MCm3,... Connected to the odd-numbered word lines WL1, WL3,. When data is transferred to the memory cells MC12 to MCm2, MC14 to MCm4,... Connected to the numbered word lines WL2, WL4,..., The control signal WT2 is set to the H level. At time t13, when the input data DI1 to DIm stored in the write register group 17 are transferred all at once to the memory cells MC1n to MCmn connected to the word line WLn, the memory cell array 11 completes the transfer of the input data DI1 to DIm. By this transfer operation, the input data DI1 to DIm are stored in the memory cells MC11 to MCm1, MC13 to MCm3,... Connected to the odd numbered word lines WL1, WL3,. The memory cells MC12 to MCm2, MC14 to MCm4,... Connected to the lines WL2, WL4,... Store the logic level inversion data / DI1 to / DIm of the input data DI1 to DIm. .

  The serial access memory 301 according to the present embodiment performs a test read operation substantially the same as the serial access memory 201 according to the second embodiment, following the test write operation.

  As described above, according to the configuration of the serial access memory 301 shown in FIG. 7 and its test write operation, it is connected to one word line as in the test write operation of the serial access memory 201 according to the second embodiment. Each memory cell stores data obtained by inverting the logic level of the data stored in each memory cell connected to the adjacent word line. Moreover, according to the configuration of the serial access memory 301 and the test write / read operation according to the present embodiment, if the storage operation of the input data DI1 to DIm for the write register group 17 is performed only once, the adjacent word line It is possible to store a data string whose logic level is inverted every time, and to read and compare the data string. Therefore, in a shorter time than the test write / read operation of the serial access memory 201 according to the second embodiment, it is determined whether or not data is normally stored in each memory cell, and the word It is possible to determine whether or not the line is selected normally.

[Fourth Embodiment] FIG. 8 shows the configuration of a serial access memory 401 according to a fourth embodiment of the present invention.

  The serial access memory 401 according to the present embodiment is different from the serial access memory 201 according to the second embodiment in the test write Y address means 411, inverters 413-1 to 413-m (m number), NOR. Gates 415-1 to 415-m (m) are added.

  The gates of the two transistors constituting each write side second transfer means 18-1 to 18-m are connected to the output terminals of the inverters 413-1 to 413-m.

  The output terminals of the NOR gates 415-1 to 415-m are connected to the input terminals of the inverters 413-1 to 413-m. The first input terminals of the NOR gates 415-1 to 415-m are connected to the transmission lines for the write Y address signals YW1 to YWm output from the write Y address means 14.

  The NOR gates 415-1 to 415-m are grouped by four. The second input terminals of the NOR gates 415-1 to 415-4 belonging to the first group are shared and connected to the transmission line of the test write Y address signal TYW1 output from the test write Y address means 411. . Similarly, the NOR gates 415-5 to 415-m belonging to each group from the second group to the k-th group (k = m / 4) have a common second input terminal for each group, and each of the test write Y The test write Y address signals TYW2 to TYWk output from the address means 411 are connected to the transmission line.

  The operation of the serial access memory 401 according to this embodiment configured as described above will be described. The serial access memory 401 is configured for the purpose of further reducing the time required for the test write operation compared to the serial access memory 201 according to the second embodiment. Therefore, here, the test write operation of the serial access memory 401 will be mainly described.

  When the test write operation is performed in the serial access memory 401, the write Y address signals YW1 to YWm output from the write Y address means 14 are all fixed at the L level. Then, the test write Y address means 411 sequentially selects the test write Y address signals TYW1 to YWk in synchronization with the clock signal CLK and sets them to the H level. At this time, input data DI1 to DIk are sequentially input to the input terminal DIN, and each input data DI1 to DIk is stored in the write registers Wreg-1 to Wreg-m. With this storing operation, the same input data is stored in each of the write registers Wreg-1 to Wreg-m. For example, the input data DI1 is input to the write registers Wreg-1 to Wreg-4, and the input data DIk is input to the write registers Wreg-m-3 to Wreg-m.

  After the input data DI1 to DIk are transferred to the write registers Wreg-1 to Wreg-m, the serial access memory 401 according to this embodiment is substantially the same test as the serial access memory 201 according to the second embodiment. Perform a write operation. That is, the control signal WT is set to H level by the memory control unit 112, and the word lines WL1 to WLn are sequentially set to H level by the X address means 13. Then, the input data DI1 to DIk stored in the write register group 17 are transferred to the memory cells MC11 to MCn connected to the word lines WL1 to WLn via the write side first transfer means 16-1 to 16-m. MCm1,..., MC1n to MCmn are transferred for each word line.

  As described above, according to the serial access memory 401 according to the present embodiment, the data length of the input data DI1 to DIk input is the same as that of the input data DI1 to DIm input to the serial access memory 201 according to the second embodiment. 1/4 of the data length. Further, the time required for storing the input data DI1 to DIk in the write registers Wreg-1 to Wreg-m is also reduced to ¼, and as a result, the time required for the test operation is shortened. In the serial access memory 401 according to the present embodiment, the NOR gates 415-1 to 415-m are grouped into four groups, but the number of groups is preferably increased or decreased according to the test contents. .

[Fifth Embodiment] FIG. 9 shows the configuration of a serial access memory 501 according to a fifth embodiment of the present invention.

  The serial access memory 501 according to the present embodiment is different from the serial access memory 201 according to the second embodiment in the write side fourth transfer means group 511 and the write data bus disconnect means 513-1 to 513 -m. , Inverters 515-1 to 515-m (m pieces), and NOR gates 517-1 to 517-m (m pieces) are added.

  The write-side fourth transfer means group 511 includes write-side fourth transfer means 511-1 to 511-m corresponding to the write registers Wreg-1 to Wreg-m. Each write-side fourth transfer means 511-1 to 511-m includes two transistors and an inverter. For example, one of the transistors constituting the write side fourth transfer means 511-1 receives the write Y address signal YW1 output from the write Y address means 14 via the drain / source thereof. 1 is transmitted. The inverter constituting the write side fourth transfer means 511-1 inverts the logic level of the write Y address signal YW1 output from the write Y address means 14 to generate an inverted write Y address signal / YW1. The other transistor constituting the write side fourth transfer means 511-1 transmits the inverted write Y address signal / YW1 to the write side second transfer means 18-1 via its drain and source. The 2 · m transistors constituting the write side fourth transfer means 511-1 to 511-m are ON / OFF controlled by the control signal TWA.

  The gates of the two transistors constituting each write side second transfer means 18-1 to 18-m are connected to the output terminals of the inverters 515-1 to 515-m. The input terminals of the inverters 515-1 to 515-m are connected to the output terminals of the NOR gates 517-1 to 517-m.

  The first input terminals of the NOR gates 517-1 to 517-m are shared and connected to the transmission line of the control signal TWA. The second input terminals of the NOR gates 517-1 to 517-m are connected to the transmission lines of the write Y address signals YW1 to YWm output from the write Y address means 14.

  Each of the write data bus disconnecting means 513-1 to 513 -m is composed of two transfer gates and an inverter. A control signal WDC is commonly input to each first control terminal of the two transfer gates, and a logic level inversion signal of the control signal WDC is commonly input to each second control terminal via an inverter. When an H level control signal WDC is input to the write data bus disconnecting means 513-1 to 513 -m, the write data buses WD and / WD are disconnected from the input / output means 122.

  The test write operation of the serial access memory 501 according to this embodiment configured as described above will be described.

  FIG. 10 is a timing chart showing the test write operation of the serial access memory 501. Hereinafter, the test write operation will be described for each time in the figure.

  <Time t1> When the test write operation is started, the H level control signal WDC is input to the write data bus disconnecting means 513, and the write data buses WD and / WD are disconnected from the input / output means 122. At the rising timing of the clock signal CLK, an H level write address enable signal WADE is input to the memory control unit 112. The memory control unit 112 instructs the write Y address means 14 to output the H level write Y address signal YW1 and the L level write Y address signals YW2 to YWm.

  Subsequently, the control signal TWA generated from the clock signal CLK becomes H level. By this H level control signal TWA, 2 · m transistors constituting the write side fourth transfer means 511-1 to 511-m are all turned on. In addition, since the second input terminals of the NOR gates 517-1 to 517-m are at the H level, all the 2 · m transistors constituting the write side second transfer means 18-1 to 18-m are also in the ON state. It becomes. Therefore, the write registers Wreg-1 to Wreg-m store the write Y address signals YW1 to YWm output from the write Y address means 14 as data. As described above, since only the write Y address signal YW1 is at the H level and the other write Y address signals YW2 to YWm are at the L level, the data "1" is stored in the write register Wreg-1, and the write register Data “0” is stored in all of Wreg-2 to Wreg-m.

  <Time t2> The word line WL1 is set to the H level by the X address means 13. As a result, the data stored in the write register group 17 is transferred all at once to the memory cells MC11 to MCm1 connected to the word line WL1.

  <Time t3> In accordance with an instruction from the memory control unit 112, the write Y address means 14 outputs an H level write Y address signal YW2 and L level write Y address signals YW1, YW3 to YWm. Since the control signal TWA becomes H level, the data “1” is stored in the write register Wreg-2, and the data “0” is stored in all the write registers Wreg-1, Wreg-2 to Wreg-m. The

  <Time t4> The word line WL2 is set to the H level by the X address means 13. As a result, the data stored in the write register group 17 is transferred all at once to the memory cells MC12 to MCm2 connected to the word line WL2.

  <Time t4 to t6> Similar to the operation from time t1 to time t4, the write Y address signals YW3 to YWm output from the write Y address means 14 are sequentially set to the H level. The write registers Wreg-1 to Wreg-m store the write Y address signals YW1 to YWm output from the write Y address means 14 as data. Further, the data stored in the write register group 17 is transferred all at once to the memory cells MC13 to MCm3,..., MC1n to MCmn connected to the word lines WL3 to WLn. At time t6, when the data stored in the write register group 17 is transferred all at once to the memory cells MC1n to MCmn connected to the word line WLn, a series of test write operations is completed.

  As described above, according to the configuration of the serial access memory 501 and the test write operation according to the present embodiment, in the m memory cells connected to each word line, only data “1” is stored in one memory cell. Is stored, and data “0” is stored in all other memory cells. When the memory cells MC11 to MCmn constituting the memory cell array 11 are viewed as a matrix, data “1” is stored diagonally with respect to this matrix.

  When serially transferring data from a write register to a memory cell array or transferring data from a memory cell array to a read register in a serial access memory, the potential difference between the power supply and ground may be reduced. . In general, this phenomenon becomes significant when data of a pattern having a logic level different from that of other bits is transferred by one bit. According to the test write operation of the serial access memory 501 according to the present embodiment, data of a pattern having a logic level different from that of the other bits by one bit is stored in the memory cell array 11, so that the data at the time of data transfer It is possible to check the so-called data transfer margin by measuring the potential change. In the serial access memory 501 according to the present embodiment, data “1” is stored diagonally in the memory cell array 11, but data “0” may be stored diagonally.

  Further, according to the serial access memory 501 of the present embodiment, the write Y address signals YW1 to YWm output from the write Y address means 14 are stored as data for each of the write registers Wreg-1 to Wreg-m. Therefore, it is not necessary to input input data from the outside during the test write operation, and the test time can be further reduced as compared with the serial access memories 101 to 401 according to the first to fourth embodiments.

  The preferred embodiments of the present invention have been described with reference to the accompanying drawings, but the present invention is not limited to such embodiments. It will be obvious to those skilled in the art that various changes or modifications can be conceived within the scope of the technical idea described in the claims, and these are naturally within the technical scope of the present invention. It is understood that it belongs.

1 is a circuit diagram showing a configuration of a serial access memory according to a first embodiment of the present invention. 3 is a timing chart showing a test write operation of the serial access memory of FIG. 1. 3 is a timing chart showing a test read operation of the serial access memory of FIG. 1. It is a circuit diagram which shows the structure of the serial access memory concerning the 2nd Embodiment of this invention. 5 is a timing chart showing a test write operation of the serial access memory of FIG. 4. It is a circuit diagram which shows the structure of the serial access memory concerning the 3rd Embodiment of this invention. 7 is a timing chart showing a test write operation of the serial access memory of FIG. 6. It is a circuit diagram which shows the structure of the serial access memory concerning the 4th Embodiment of this invention. It is a circuit diagram which shows the structure of the serial access memory concerning the 5th Embodiment of this invention. 10 is a timing chart showing a test write operation of the serial access memory of FIG. 9. It is a circuit diagram which shows the structure of the conventional serial access memory. 12 is a timing chart showing a write operation of the serial access memory of FIG. 12 is a timing chart showing a read operation of the serial access memory of FIG.

Explanation of symbols

11: Memory cell array 13: X address means 14: Write Y address means 15: Read Y address means 16: Write side first transfer means group 16-1 to 16-m: Write side first transfer means 17: Write register group 18 : Write side second transfer means group 18-1 to 18-m: Write side second transfer means 19: Read side first transfer means group 19-1 to 19-m: Read side first transfer means 20: Read register group 21: Read side second transfer means group 21-1 to 21-m: Read side second transfer means 101, 201, 301, 401: Serial access memory 112: Memory control unit 122: Input / output means 123: Output means 211, 212: Inverter 311: Write side third transfer means group 311-1 to 311-m: Write side third transfer means 411 Test write Y address means 413-1 to 413-m: inverters 415-1 to 415-m: NOR gate 511: write-side fourth transfer means group 511-1 to 511-m: write-side fourth transfer means 513: Write data bus disconnecting means 515-1 to 515-m: inverters 517-1 to 517-m: NOR gates BL1, / BL1 to BLm, / BLm: bit line pairs CLK: clock signals DI1 to DIm: input data DO1 DOm: Output data MC11 to MCmn: Memory cell RADE: Read address enable signal RD, / RD: Read data bus RE: Read enable signal Rreg-1 to Rreg-m: Read register RT: Control signal RXAD: Read X address TM: Test mode signal TWA: Control signals TYW1 to TYWk: Te Write Y address signal WADE: Write address enable signal WDC: Control signals WD, / WD: Write data bus WE: Write enable signals WL1 to WLn: Word line WR: Write reset signals Wreg-1 to Wreg-m: Write register WT: Control signal WT2: Control signal WXAD: Write X address YR1-YRm: Read Y address signal YW1-YWm: Write Y address signal

Claims (5)

A memory cell array having a plurality of word lines, a plurality of bit lines , and a plurality of memory cells arranged at intersections of the word lines and the bit lines ;
A first register for storing data stored in a plurality of memory cells connected to each word line;
A second register for storing data stored in a plurality of memory cells connected to each word line;
A data input terminal to which input data is input;
Input / output means connected to the data input terminal and the first data bus;
Connected to the first data bus and the first register, and transfers data on the first data bus to the first register or in the first register in response to a first transfer control signal A first transfer gate for transferring data to the first data bus;
A data output terminal for outputting output data;
Output means connected to the data output terminal and a second data bus;
A second transfer gate connected to the second data bus and the second register and transferring data in the second register to the second data bus in response to a second transfer control signal;
A third data bus provided separately from the bit line , connected to the input / output means and the output means and transferring data received by the input / output means to the output means;
And the output means compares the data received from the second register with the data received from the input / output means.
  The serial access memory according to claim 1, wherein the third data bus is connected to an inverter having the input / output means side as an input and the output means side as an output. The first register includes a plurality of first storage units provided corresponding to the plurality of bit lines, and the first transfer gate includes a plurality of first storage units of the first register. And the second register includes a plurality of second storage units provided corresponding to the plurality of bit lines, and the second transfer. The gate has a plurality of second gates provided corresponding to each of the plurality of second storage units of the second register, and the first and second transfer control signals are respectively the first and second transfer control signals. 2. The serial access memory according to claim 1, comprising a plurality of signals corresponding to the second storage unit. And X addressing means for driving each said plurality of word lines, said plurality of first and Y addressing means for writing to output a transfer control signal, the read Y address means for outputting said plurality of second transfer control signal serial access memory according to claim 3, wherein you characterized in that have a. X address means for driving each of the plurality of word lines, write Y address means for outputting the plurality of third transfer control signals, and read Y address means for outputting the plurality of second transfer control signals And receiving the plurality of third transfer control signals and the fourth transfer control signal, and based on the plurality of third transfer control signals and the fourth transfer control signal, the plurality of first transfer control signals. A transfer control signal is generated, and is the same for a predetermined number of the plurality of first transfer control signals regardless of the state of the third transfer control signal according to the state of the fourth transfer control signal. 4. The serial access memory according to claim 3, further comprising: a transfer signal generation unit that outputs as a state; and a test write Y address unit that outputs the fourth transfer control signal.

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