SU1361631A2 - Read-only memory - Google Patents

Abstract

The invention relates to computing and is intended for the construction of permanent storage devices. The purpose of the invention is to increase the speed of a persistent storage device. The goal is accomplished by reading information from memory modules managed by a driver that minimizes address sampling, which increases the speed of the device. And only by the addresses that the memory drivers and memory modules they control switch to, the time for reading information from memory modules increases by the rise time of the front switched on driver, by the recovery time of the memory chip when the power is turned on, by the fall time of the front off aemogo shaper and recovery time disables operability of memory. The device contains a drive 1, memory modules 2, registers 3,4,7,11 addresses, decoders 5.8, register 6 signs, drivers 9, power source 10, elements 12 and 13 of comparison and delay. 1 il. (A) Has ZfO CD OS stopped since

Description

1136

The invention relates to computing technology, is designed to construct permanent storage devices with low power consumption and high speed and is an improvement of the invention in accordance with the author. No. 746730,

The purpose of the invention is to increase the speed of the device.

The drawing shows a block diagram of a permanent post. storage device.

The device contains a drive 1, the state PAIDs from storage modules 2, the first 3 and second 4 registers of the address, the first decoder 5, register 6 signs, the third register 7 addresses, the second decoder 8, drivers 9, the first power source (not shown), the second source 10 power, fourth address register 11, elements 12 and 13 of comparison and delay, respectively.

The device works as follows.

In the initial state, power is supplied to the registers 3, 4, 6, 7 and 11, elements 12 and 13, decoders 5 and 8, and drivers 9. The address from register 7 is fed to register 11 and to the input of element 12. Continuous power The E is fed through the selected driver to the memory devices connected to it. Whether or not the read information from the storage module by the strobe is rewritten into register b, where it is stored for the required time.

When a new address arrives at registers 3, 4 and 7 (register 7 controls the decoder of drivers), a comparison of the address received to register 7 and the stored previous address in register 11 on element 12 occurs. In the case of the comparison of addresses, the previously selected driver remains with open, information is read from the same memory modules as in the previous call. In the case of non-matching of addresses from registers 7 and 11, on element 12, a Stop signal is generated, which goes to the central processor and prohibits turning e in a permanent storage device. The same signal enters the register 6 and prohibits the issuance of unspecified information to the mainline of the computer if the machine performs other operations at this point in time. If the computer works in

one

asynchronous mode, it will suffice to give a signal to stop the register 6.

Signal generation Stop occurs as follows. An incomparable signal from element 12 triggers element 13, which forms the duration of the stop signal, which is determined by the duration of transients that occur when switching the drivers 9 and modules 2. The trailing edge of the signal Stop in register 11 records the address from register 7, element 12 is set to Comparison. The new driver 9 chosen by the decoder 8 supplies a constant voltage to the memory modules connected to it. At the end of the Stop signal, information is stored from the permanent storage device corresponding to the new address.

Introduction of new elements allows, within the operating time of each generator (i.e., when reading information for several cycles from the same storage modules) to read information from the storage modules managed by it with a minimum sample equal to the address sampling time , - specified in the specifications of the memory chip, which increases the speed of the device. And only at the addresses at which the shapers and the memory modules managed by them switch, the time for reading information from the memory modules is increased by the rise time of the front shaper switched on, the recovery time of the memory chip when the power is turned on, the fall of the front shaper front side and recovery time off memory modules. I

Claims (1)

Claims. Permanent memory device auth.St. No. 746730, characterized in that, in order to increase the speed of the device, a comparison element, a delay element, the fourth address register, whose control and information inputs are connected to the delay element output and output, are entered into it. 31361631 of the third address register connected to the input of the delay element with the first input of the element with the comparative second information input of the register, the second input of which of the subgroup signs is the second input to the output of the fourth register with the addendum of the constant charge, the output element of the comparison of the reference device.