SU1566413A1 - Permanent memory with self-check - Google Patents

Abstract

The invention relates to computing and can be used to control the functioning of permanent storage devices during operation. The aim of the invention is to increase the reliability of the operation of a persistent storage device. The self-monitoring permanent memory contains an address counter, a first comparison unit, a signature analyzer. Introduction to the device of two elements And, the second comparison unit, the memory unit, the delay element, the register of reference signatures, the control trigger allows the wire to monitor the permanent storage devices during operation, thereby increasing the reliability of the output information. 2 Il.

Description

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The invention relates to computing and can be used to control the functioning of permanent storage devices during operation.

The purpose of the invention is to increase the reliability of the operation of a persistent storage device.

FIG. 1 is a block diagram of a self-monitoring permanent storage device; in fig. 2 - parallel register signatures.

Permanent self-monitoring memory device contains device address inputs 1, device operation mode setting input 2, device 3 reference signatures input, sync input 4, first element 5, second second 6, register 7 reference signature, address counter 8 memory block 9 , delay element 10, first comparison block 11, signature analyzer 12, second comparison block 13, control trigger 14,

information outputs 15. output of 16 work ends, output 17 of the control result, trigger 18, adders 19 and 20 modulo two

Permanent self-monitoring memory device operates as follows.

Before starting the operation, the counter 8 is set to zero, and the trigger 14 is set to one (the reset circuits are not shown), the reference signature corresponding to this ROM is written to the register of the reference signatures.

The signature analyzer is a known device.

Memory block 9 is made on ROM cells.

The monitoring process is carried out as follows. When the address on the address bus 1 coincides with the value of the address 8 counter, the comparison unit 13 is triggered and the access signal from the input 2 of the assignment mode

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with

This work takes place at the synchronization input of the signature analyzer 12, thereby recording the contents of the zero cell. At the same time, the contents of the counter 8 increase. The next time the addresses on address bus 1 match and the outputs of counter 8, the data read from the ROM is written to the signature analyzer 12. When the counter 8 of the address overflows, the signature generated by the signature analyzer is compared with the reference value, written in the register of 7 reference signatures. In the case of non-comparison, the control trigger 14 switches to the zero state, the first element And 5 closes, thereby stopping the operation of the device.

The application of the proposed device allows the wire monitoring of permanent storage devices in operation, thereby to increase the reliability of data read from the ROM.

Claims (1)

The invention A permanent self-monitoring memory device containing an address counter, a first comparison unit, a signature analyzer whose information inputs are connected to the outputs of the memory block and are information outputs of the device, the inputs of the first group of the first comparison block are connected to the outputs of the signature analyzer, furthermore, in order to increase the reliability of the operation of the persistent storage device, the register of reference signatures is entered into the device, the second block comparison, control trigger, delay element, first and second elements AND, the information inputs of the register of reference signatures being inputs of reference signatures of the device, the synchronization input of the register of reference signatures is a synchronous input, the outputs of the register of reference signatures are connected to the inputs of the second group of the first comparison unit, the output of which is connected to the information input of the control trigger, the synchronization input of which is connected to the overflow output of the address counter and is the output of the device operation end, the output of the control trigger is connected to the second input of the first AND element and is the output of the device control result, the first input of the first element I is the input of setting the operation mode of the device, the output of the first element I is connected to the first input of the second element AND and the input setting the mode of the memory block, the output of the second ele And is connected to the synchronization input of the address counter and the input of the delay element, the output of which is connected to the synchronization input of the signature analyzer, the information outputs of the address counter are connected to the inputs of the second group of the second comparison unit, the output of which is connected to the second input of the second element, the address inputs of the memory block are connected to the inputs of the first group of the second comparison unit and are address inputs devices. 1