SU1361589A1 - Mage identification device - Google Patents

Abstract

The invention relates to automation and computing, and can be used to control the quality of precision tape mechanisms, for example, to detect poor-quality rotating units or vibrating guides, or racks. The aim of the invention is to improve the reliability of the device. This goal is achieved in a device containing a sensor unit, an amplifier unit, an analog-to-digital converter, a control unit, a calculator, three memory blocks, an OR-NOT element, and indicators, by introducing the first filter to the second filter. elements, detector, differentials element, first and second keys, voltage sources, OR element, trigger, pulse shaper, decoder, first, second and third counters, inverter, 11PI element block, first and second delay elements, adder , block constant n amti and switch. 1 hp f-ly, 3 ill. (L (U) sd 00 x

Description

The invention relates to automation and computing and can be used, in particular, to control the quality of precision tape-type mechanisms.

The purpose of the invention is to increase the reliability of recognition.

FIG. 1 shows a block diagram of the device; in fig. 2 is a control block diagram; in fig. 3 is an example of a specific implementation of a trigger.

The device (Fig. 1) contains a block of 1 signal sensors, an amplifier unit 2, the first 3, the second A and the third 5 memory blocks, the analog-to-digital converter (ADC) 6, the control unit 7, the subtractor 8, the indicators 9, the RSHI element NOT 10, switch 11, first 12 and second 13 filter elements, detector 14, differentiating element 15, first 16 and second 17 keys, first 18 and second 19 comparators, first 20 and second 21 reference voltage sources, OR 22 element, trigger 23, pulse shaper 24, decoder 25, first 26, second 27 and third 28 counters, inverter 29, unit 30 ale ntov OR, the first 31 and second 32 delay elements, the adder 33 and. fixed memory unit 34.

The control unit 7 (Fig. 2) contains the first 35 and second 36 triggers, the first 37, the second 38 and the third 39 elements AND, the first 40 and the second 41 elements OR, the switch 42, made in the form of a dual toggle switch, and the pulse generator 43. Switch 42 is shown in the Training position.

The trigger 23 (Fig. 3) consists of a dynamic trigger 44 and the element And 45.

The device works as follows.

In the mode of learning to recognize objects, for example, precision tape-moving mechanisms with moving nodes, sensors are mounted in the object of recognition. Sensors can be of different designs, reacting, for example, to mechanical excitations, accelerations, movements or reacting to acoustic signals in three mutually perpendicular coordinates. Sensors should be located in the most critical areas of the object being diagnosed.

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or in places experimentally chosen to recognize the largest possible number of possible states of the object being diagnosed.

The learning process begins with a pulse. Start at the first input of the device. On this signal, the first 26 and second 27 counters are set to zero and the triggers 35 and 36 of the control unit 7 are set to one, and the trigger 36 is set to one by the leading edge of the signal from the output of the trigger 35. In addition, the forward the front of this pulse shaper 24 generates a pulse, which is preparing the ADC 6 and the trigger 23 (figure 3) to work. For the duration of the pulse from the output of the former 24, the first switch 16 transmits to its output a first reference voltage, which is obviously taken greater than the second reference voltage. The first comparator 18 in this case has zero potential at its output. At the end of the pulse time from the output of the imager 24, the first key 16 switches to its output the voltage from the output of the differentiating element 15. When the voltage value at the output of the differentiating element 15 becomes less than the second reference voltage, the trigger 23 is set to one a state with a positive front from the output of the first comparator 18 and starts the ADC 6 with the leading edge of its output signal. The need to determine the instant of a steady signal at the output of the second filter element 13 is caused by the presence of transients in the measured signal when switching signals from the sensor unit 1 using switch 11 and switching individual bands of the first filter element 12.

Three signals from block 1 at coordinates X, Y, and Z are amplified by block 2 amplifiers and fed to analog switch 11, which passes only one of the input signals to its output, depending on the state of counter 26 decoded by decoder 25. This signal goes to the first filter element 12, made in the form of a controlled filter bank. The amplitude-frequency characteristic of this filter element is adjustable and passes only a certain part of the spectrum of the input signal, depending on the code at the output of counter 27. The envelope on detector 14 is selected from the selected part of the spectrum of the input signal and the carrier filter 13 is filtered made in the form of a lowpass filter. The voltage from the output of the second element 13 goes to the ADC 6, where it converts to a digital code on the leading edge of the signal from the output of the trigger 23. After the conversion is completed, the ADC 6 generates a positive front at the second output, which through the third input of the control unit 7 open element 39 at the input of switch 42 passes to the second output of control unit 7. This signal is then fed to the synchronization input of the second memory block 4. On its leading edge, a digital code is written from the output of the ADC 6 to the corresponding memory cell. The cell address of memory block 4 is determined by the digital code on the second counter 27, the enabling signal at one of the outputs of the decoder 25, and the code at the output of block 30 of the OR elements. The code at the output of block 30 repeats the code at the output of the second key 17 opened by the enable signal from the fourth output of the control block 7, and therefore the code set manually on the first input group of the device goes to the third group of address inputs of the second memory block 4. When training, sensors are installed on the object, in the pre-selected places, and the image code is installed on the first group of device inputs.

Block 30 of the OR elements performs the disjunction of the signals from the corresponding outputs of the second key 17 and the third counter 28. In the cpu mode, i.e. recording information into the second memory block 4, the third counter 28 is in the zero state under the influence of the signal from the output of the inverter 29 and, therefore, the outputs of the OR block of the OR elements have the code of the first group of device inputs. In the recognition mode, the second key 17

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it is closed by a zero signal from the fourth output of the control block-7 and, therefore, there are no signals at the output of the second key 17. This is due to the fact that the second key 17 is not a storage device, but is implemented on the basis of combinatorial logic. When the left signal is applied to the control input on the inputs of the OR-YE elements, there is a zero signal that does not interfere (passing the counter code 28 through the block 30 elements OR to the address inputs of the memory blocks 4. On the leading edge of the conversion end signal from the service output of the ADC 6 impulse passes through the open resolving potential of the trigger 36 element 38 AND through the element OR 41 of the control unit 7 to the counting input of the first counter 26, switching it to the next state. The position of the resolving potential changes accordingly

5 at the output of the decoder 25, which connects the signal from another sensor to the output of switch 11. In addition, the leading edge from the service output of the A / D converter 6 also generates a pulse on the leading edge from the service output of the ADC 6, the duration of which is equal to the time of recording information into the second memory block 4. On the falling edge of this pulse, ACC 6 and trigger 23 are reset, preparing them for the next survey.

When polling all sensors in the same frequency range, an overflow pulse from the output of the first counter 26 switches the second counter 27 to the next state. Thus, all sensors are polled over all frequency ranges, and their digital readings are stored in the second memory block 4. When the last sensor is polled over the last frequency range, the overflow pulse from the output of the second counter 27 goes to the second input of the control unit 7, where sets the triggers 35 and 36 to the initial state, thereby removing the permission for the memory unit to work, and by prohibiting the installation of the trigger 23 in the single state, it prohibits the operation of the ADC 6. The zero level of the signal from the trigger output 36 akryvaet AND gate 38 to inhibit the passage of pulses to the input of the first counter 26. The output of the last code is not changed and

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The sampling address of the second memory block 4 does not change. This occurs at the end of the training of an individual image and practically means the end of the operation of memory block 4. After this, the image of the object under study is changed and the learning process is repeated by applying a Start pulse to the first input of the device. After training on all the possible foreseen states of the monitored object, the learning process ends. .

In the pattern recognition mode of the object under study, the switch 42 of the control unit 7 is switched to the Recognition mode. This closes the second key 17, prohibiting the external installation of the image number of the object under study, and the element 39 is closed, prohibiting the supply of write synchronization pulses to the second memory block 4. In addition, the recognition process ends only when all the memory cells of all samples of the object under study in the second memory block 4 are polled. For this, the overflow pulse from the output of the second counter 27 is fed to the counting input of the third counter 28 by switching the toggle switch 42. In this case, the flip-flop 35 is reset by the overflow pulse of the third counter 28.

The recognition process also begins by installing the sensors of unit 1 in the object under study, which is to be monitored. When a pulse is applied, the process of interrogating sensors, similar to the Training mode, begins at the first input of the device. However, the digital data of the object under investigation is recorded in the first memory block -3. When all sensors are polled over all frequency bands, the overflow pulse from the second counter 27 triggers 36 to its initial state. In this case, the device switches to the mode of comparing the received data with the data stored in the second memory block 4. At the same time, the permitting potentials arriving at AND 37 open it and enable the generator 43 to work. In addition, the resolving potential output of the control unit 7 puts the first 3 and second 4 memory blocks into read-out mode and at the same time the installation the trigger 23 into the unit state by applying a positive level to the inverse input of setting it to zero from the first output of the control unit 7. The pulses from the generator 43, acting on the first counter 26 and further on the second 27 and third 28 counters,

0 interrogate cells of blocks 3 and 4 of memory. In this case, when reading information from the memory cells of the same name of the first memory block 3, in which there is information about

5 object, and the second memory block 4, in which the reference data about this object, obtained during training, is stored, it is fed to separate inputs of the slider 8. The difference between

0, in absolute value, is fed to the information input of the adder 33, to the counting input of which, via the delay element 32, a pulse is fed from the generator 43, summing the information stored in the adder 33 with a digital code from the subtractor output. The delay time of delay element 32 is chosen longer than the time for setting counters 26 and 27,

0 decoder 25, blocks 3 and 4 of memory and subtractor 8.

When comparing the values of the memory cells of the first memory block 3 with the values of the memory cells of memory block 4, there is a number at the output of the adder indicating the degree of divergence of the object under study with the compared (reference) object. This number is compared with the number stored in block 34, on the second digital comparator 19. If it is less than this number, a decision is made about the coincidence of the object under study with this image and its output is a logical one. Otherwise, this does not happen. The pulse is full, nor from the second counter 27 is fed to the input of the reception of the third memory block 5, recorded at the address determined by the code on the third counter 28, the signal from the output of the second comparator 19. The overflow pulse from the output of the second counter 27 through the element 31 delays are fed to the zeroing input of the adder 33. This impulse is also fed through the closed contacts of the switch 42 to the fifth output of the control unit 7 and then to the counting input of the third counter 28,

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switching it to the next state. The process of comparing the data of the first 3 blocks of memory with other data of the memory of block 4 of the memory continues.

Upon completion of the data comparison process, the overflow pulse from the third counter 28 through the OR 40 element sets the trigger 35 of the control unit 7 to the initial state, stopping the operation of the entire device. In this case, one of the indicators 9 shows the corresponding indication of the object. If none of the images previously recorded in block 4 of the memory does not coincide with the image of the object being investigated, a logical unit appears at the output of the element OR NOT 10, including one of the indicators 9, denoting the unidentified image of the volume, which is necessary later on analyze and, if necessary, write its data into separate cells of memory block 4. In order to eliminate the indication of the last situation in the process of comparing data, the element OR NOT 10 is closed by a logical unit from the seventh output of the control unit 7. When the next start signal is applied, the third memory block 5 is zeroed on the leading edge of the signal from the seventh output of the control block 7.

Inverter 29 is intended for off; Turning off the third counter 28 by supplying a high level to its reset input, made potential, in the mode of recording information in blocks 3 and 4 of memory. The latter are made with multiple addressing. At the same time, the digital address codes from the second counter 27 and the block 30 of the OR elements are fed to different inputs of the standard memory block. The signals from the output of the decoder 25 select a specific chip from memory blocks 3 and 4 by applying an enable signal to the input Selecting an IC for only one chip.

The proposed solution has advantages over the known ones associated with interrogating sensors in mutually perpendicular directions and different frequency ranges, i.e. practically in this device, the spectral characteristic of the object is measured in three coordinates, which is compared with the spectral. Noah characteristic known about: raig

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behind. Because of the extreme, the reliability of pattern recognition, for example, not perfectly rotating parts of vibrating struts and guides and similar nodes and blocks in tape mechanisms that have their own spectrum in different spatial directions of signals during operation or excitation, is significantly increased. Moreover, a normally working object is also taken as a separate image. In addition, the device eliminates cognition errors associated with transients in the objects under study.

Claims (2)

1. A device for pattern recognition, comprising a block of sensors, the outputs of which are connected to the inputs of the amplifier unit, the first and second blocks of memory, the information inputs of which are connected to the first output of the analog-digital converter, the readings input - to the first output of the control unit, and the outputs are connected with information inputs subtracted body, the third memory block whose outputs are connected to the inputs of the indicator group and to one of the inputs of the IL-NOT element whose output is connected; (yen with an additional indicator, the second output of the control unit is connected to the clock input of the second memory block, the first control the input of the control unit is the first input of the device, and the second control input of the control unit is connected to the receive input of the third memory block, the address inputs of which are connected to the first address inputs of the second memory block, right now with that in order to improve the reliability of the device, it contains the first and second filtering elements, the detector, the differentiating element, the first and second keys, the first and second switches, the first and second sources of the reference voltage, the OR element, the trigger, the pulse shaper, the decoder, the first, second and the third counters, an inverter, an OR block, the first and second delay elements, an adder, a permanent memory block and a switch, whose information inputs are connected to the outputs of the amplifier block, and the output 9 . . 1 is connected to the information input of the first filter element, the output of which is connected to the detector input, the output of which is connected to the input of the second filter element, the output of which is connected to the analog input of the analog-digital converter and to the input of the differentiating element whose output is connected to the first analog input of the first key, The second analog input of which is connected to the output of the first voltage source, and the output - to the first analog input of the first comparator, the second analog input of which connected to the output of the second voltage source, and the output to the setup input of the trigger, the output of which is connected to the trigger input of the analog-digital converter, a potential trigger reset input connected to the first output of the control unit, a dynamic trigger reset input connected to the trigger the key input and the reset input of the analog-digital converter is connected to the output of the pulse former, the input of which is connected to the output of the OR element, the first input of which is connected to the clock input of the transducer The third memory block and the third input of the control unit are connected to the second output of the analog-digital converter, the control input of the switch is connected to the first address input of the first memory block, the second address input of the second memory block, and the output of the decoder whose input is connected to the output of the first a counter whose input is connected to the third output of the control unit, and the overflow output of the first counter is connected to the counting input of the second counter, the output of which is connected to the control input of the first filter element, with the second address input of the first memory block and with the third address input of the second memory block, the overflow output of the second counter is connected to the second control input of the control unit and to the input of the first delay element whose output is connected to the reset input of the adder, the fourth output of the control unit is connected to the control input of the second key, the inputs of which are the second input of the device and the output 61589 10 is connected to the first input of an OR unit, the second input of which is connected to the output of the third counter, the counting input of which is connected to the fifth output of the control unit, the reset input to the output of the inverter, and the overflow output to the fourth input of the control unit, the first output which is connected to the inverter input, the output of the block of elements OR is connected to the first address input of the second memory block, the information input of the third memory block is connected to the output of the second comparator, the first information input of which is connected to block move constant memory and the second data input - to the output of the adder, the information The 2Q input of which is connected to the output of the subtractor, and the synchronization input.-, with the output of the second delay element, the input of which is connected to the other output of the control unit, the seventh output of which is connected to the erase input of the third memory block and to the corresponding input of the OR element , and the inputs of the installation o Oh the first and second counters and 30, the second input of the element OR is connected to the first input of the device, 2. The device according to claim 1, about the tsl and - 1 that the control unit contains the first and second triggers, the first, second and third elements And, the first and second elements OR, switch and pulse generator. The setup input of the first trigger is the first input of the block, the reset input of the first trigger is connected to the output of the first OR element, the first input of which is the fourth input of the block, the seventh output of which is the output of the first trigger connected to the first input of the first element. and to the installation dynamic input of the second trigger, the direct output of which is connected to the first input of the second element AND, the second input of which is connected to the first input of the second element OR and is the third input of the block, and the output inn with the first input of the second OR element, the output of which is the third output of the block, the inverse output of the second trigger is connected to the second input of the first And element, the output of which is the first output of the block and connected to the input of the generator 35 40 50 55 Pa pulses, the output of which is the sixth output of the block and connected to the second input of the second OR element, the first output of the switch is connected to the second input of the third And element and is the fourth output of the block, the fifth output of which is the second output of the switch, the first input of which is connected to the zero potential bus of the device, and the second input to the reset input of the first trigger is the second input of the block. / / ffx o about 35 Gh tt 3S 1 r H r 59 P w -I 42 n-t-i Editor I.Nikolaychuk Compiled by T.Nichiporovich Tehred A. Kravchuk Order 6293/50 Circulation 671-Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 ISbiK "J  rffwx 5A / X - one t 2Art Ll .2 FS / g.Z. Proofreader A. R1pyin