SU1716501A1 - Information input device - Google Patents

Abstract

The invention relates to automation and computer technology and can be used for collecting and express processing information from analog and digital sensors. The purpose of the invention is to increase the reliability of the device. The device allows input and processing of information from analog and digital sensors. The data acquisition and processing unit included in the device performs byte-by-by-by-by-minute analysis of the input information; for example, extreme, statistical, or screening of faulty information. Zil.

Description

The invention relates to automation and computing and can be used to collect and express information processing from analog and digital sensors.

The aim of the invention is to increase the reliability of the device.

FIG. 1 shows a functional diagram of the device; in fig. 2 shows an example of implementation of a RAM unit; in fig. 3 - firmware control unit.

FIG. 1 denotes analog sensors 1, block 2 normalization, analog-to-digital converter (ADC) 3, generator 4 pulses, controlled frequency divider 5, delay element 6, data bus 7, address register 8, microprogram control unit (BMU) 9 , memory unit 10, buffer memory unit 11, decoder 12, control bus 13, multiplexer 14, paraphase amplifier 15, buffer p & gistor 16, interface block 17, digital

sensors 18, block 19 of sbrr and data processing (PBCD data acquisition processor).

FIG. 2 designates two address registers 20, 21 and a memory node 22.

FIG. 3 denotes a bus driver 23, a micro-command sequence control unit 24, a micro-command address register 25, a read-only memory (ROM) 26.

The device works as follows.

Before starting the data acquisition procedure, the memory unit 10 is loaded from the central processor (external to this device). To do this, the data input of the block 10 receives data, the address input — the address of the cells of the memory block, and the record input — the recording signal. Under the influence of the write signal, the address code is transmitted through the address register 21 (FIG. 2) to the address input of the operating memory unit 22, determining the address of the cell into which the data is written. The same write signal writes data to the select;

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nuyu. cell A register 21 with three output states is disconnected from the address input of the node 22 in the absence of a write signal. As the RAM block 10, a permanent memory device (ROM) can be used, then an initial boot operation is absent. The information of block 10 determines the order of polling channels, the mode of suppression of common mode noise, the type of channel being polled (analog or 10 digital), the sampling frequency of the ADC 3, the mode of operation of block 2. The order of operation of the device is determined by the software work of EMU 9. This program is sewn into ROM 26 (Fig. 3) and contains instructions for the operation of the device blocks. At the start, the microcomputer address register 25 is reset to zero, indicating the zero memory location of block 26. C is zero; About the address of the ROM 26, there is a program 20, according to which the data collection processor 19 polls a certain cell of the block 10 and analyzes one of its bits. If the bit is set, which indicates the completion of the initial boot procedure, then the 25 processor. 19 generates a signal at the output of the zero result, having received which, the node 24 will change the contents of register 25. Thus, as soon as memory block 1Q is full, block 9 of microprogram control 30 switches to another work program, the acquisition and express processing program. As the node 24 can be used chip K1804VU4, and block 19 - K1804BC1, .35

According to the work of the device on the program of collection and express processing. The operation begins with the reading of the constant from the RAM block 10. For this, the BMU 9 exposes the address of the block 10 to the control bus 13, which is decrypted by the decoder 12. The decoder 12 generates a write pulse, which enters memory unit 10. In addition to this, the BMU 9 exposes to the processor 19 a write command, according to which the contents of one of its internal registers, in which the address of the current cell of block 10 is stored, is output to the data bus. The contents of the register go through the data bus to the input of the address register 20 50 and are written into it on the leading edge of the write pulse. From the output of the register 20, the address is supplied to the address input of the RAM node 22. In the next step, BMU

9 issues a read command for 55 to block 19 and a read signal for block 10 to bus 13. Block

The operational memory exposes to the data bus the contents of the cell whose address is recorded in register 20, and block 19 reads this data from the data buster 7. After this block

19, under the control of the BMU, 9 begins analyzing the received data. The data contains information on which of the elements 2, 5, 8, 17 is programmed. Upon completion of the analysis, block 19 informs the BMU 9 on the output of the zero result. After that, the BMU 9 sets the address of the decoder 12 to the address of one of blocks 2, 5, 8 or 17 and the write command for block 19, on which the data acquisition processor sets to the bus 7 is a constant (in the simplest case, the same as that read from block 10 of the RAM). Depending on which block is decrypted, a strobe-pulse appears on one of the outputs of the decoder 12, on the front of which the code from the data bus will be recorded in one of the blocks 2, 5, 8 or 17, determines its mode of operation. The cycle that begins reading the constant from the RAM block 10 is completed after the registers of all the above blocks are loaded. The constant recorded in the register of block 2 normalization matches the dynamic range of the signal at the input of block 2 (amplitude and offset relative to zero) with the dynamic range of the ADC 3, and in the register of the divider 5 uniquely determines the time interval between the previous and subsequent intervals of the start of the ADC 3, in register 8, the number of the connected analog channel or the number of two channels in the mode of common mode interference; in the register of the conjugate block 17, the number of the connected digital channel. If the sampling frequency of the signals of all sensors 1 is the same, then the register of the controlled frequency divider 5 should be loaded only once before starting work. The same applies to blocks 2, 8, or 17, if respectively the same dynamic range of the signals of all the interrogated analog sensors, only one analog channel, one digital channel is connected.

The signal from the sensor connected to the currently selected channel, converted in normalization block 2, is fed to the input of ADC 3. With the arrival of a trigger pulse from the output of controlled frequency divider 5, a digital code appears at the output of ADC 3 proportional to the signal voltage the entrance. The trigger pulse, delayed by the delay element 6 at the time of the conversion of the ADC, writes this code to the buffer register 16 (for example, 1533 IL 33), simultaneously a pulse. From the output of the element 6, the delay arrives at the BMU 9, an alert about data readiness;

Under control of the BMU 9, the processor 10 reads the digital code from the buffer register 16 over the data bus 7. If the program

Since BMU 9 does not provide any actions with data, then under control of block 9, processor 19 writes this code to block 11 of the buffer memory. At the same time, a ready signal appears at the output of the buffer memory unit 11, which notifies the external processor that data for reading has appeared in the device.

The mode of operation with digital channels is also set by the information recorded in the RAM block 10. In this case, there is no need to write control codes in register 8, blocks 2 and 5. It is only necessary to program the operation of block 17 of the conjugation. For this, block 9 sets on bus 13 a parallel address of this block and a write command for processor 19. After the pulse is decoded from the output of the decoder 12, the data from the processor 19 will be written to block 17, determining its mode of operation. If the device collects data from only one digital information sensor, then block 17 is programmed only once before starting work. As a unit 17, a 580BB55 microcircuit can be used, which possesses the quality of bi-directional data transmission. Thus, it is possible to adaptively: control those processes and devices to which analog and digital sensors are connected. For this, part of the digital sensors should be replaced by receivers of digital information (in the simplest case, digital-analog converters). The adaptive control scheme is as follows: collecting data from analog and digital sensors, monitoring parameters of input information that passes through processor 19, and, if necessary, issuing commands or control codes to external device actuators connected instead of some digital signals. sensors.

The use of processor 19 for byte-by-analysis of input information (extreme analysis, screening of faulty information, statistical analysis) increases the reliability of the device, combining analog and digital channels in a single device expands the possible area of its application.

Claims (1)

Invention Formula An information input device comprising a multiplexer, a normalization unit, an analog-digital converter, buffer and main memory blocks, a microprogram control unit, a decoder, a controlled frequency divider, a pulse generator, a delay element and The address register, whose outputs are connected to the address inputs of a multiplexer, whose information inputs are information analog inputs of the device, the output of the normalization unit is connected to the information input of the analog-digital converter, the output of the pulse generator is connected to the clock input of a controlled frequency divider, the output of which is connected to the input start analog-to-digital Converter and the input of the delay element, the first, second and third outputs of the decoder are connected respectively to the gate in The address of the address register, the normalization block and the controlled frequency divider, the inputs of the address register setting, the normalization block and the controlled frequency divider are combined by a bi-directional data bus with the information inputs / outputs of the microprogram control unit and the main memory unit, information outputs, read input and readiness output the buffer memory block are respectively the information outputs, the read input and the readiness output of the device, the information inputs, the address inputs of the first group and the write input The operational memory unit is, respectively, information inputs, address inputs and a device recording input, characterized in that, in order to increase the reliability of the device, it contains a interface unit, a paraphase amplifier, a buffer register and a data acquisition and processing unit. the inputs of which through the bi-directional control bus are combined with the address inputs of the second group of the RAM block, the address inputs of the interface block, the inputs of the decoder and the control inputs of the microprogram control unit , the outputs of the analog-digital converter are connected to the information inputs of the buffer register, the outputs of which are connected via the bi-directional data bus to the information inputs of the buffer memory block, information inputs / outputs of the data acquisition and processing block, information inputs-outputs of the interface block, the first and second outputs the multiplexer is connected to the inputs of a paraphase amplifier, the output of which is connected to the information input of the normalization unit; the fourth, fifth, sixth and seventh outputs of the decoder connection The inputs of the data acquisition-output of the collection and processing unit, the information inputs-outputs of the data block are connected to the input gate of the gateway, respectively, with the gating inputs of the interface unit, the buffer register, the recording input of the buffer memory block and the readiness input of the microprogrammed control unit. The information block of the firmware I / O control of the device. 20 Fi.g 21 fig.Z