SU1327123A1 - Apparatus for analysing random signals - Google Patents

Abstract

The invention relates to computing and can be used in medicine for the processing of electroencephalogram signals. The purpose of the invention is to expand the functionality due to the possibility of averaging the signal over an arbitrary number of implementations. The operation of the device is based on combining the accumulation, display, analog and digital information output modes, while ensuring the mutual independence of these modes. The device contains an analog-to-digital converter 1, an ari-ethical-logical unit 2, a memory block 3, registers 4, 14, 15, 16, a microprogram control block 5, a clock generator 6, counters 7, 11, 12, 13, digital-to-analog converters 8, 17, 18, demultiplexers 19 and 20, multiplexer 21. The device allows to process signals, eliminating myMt by averaging the signal over an ensemble of 1 hp realizations. f-ly, 3 ill. S O)

Description

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The invention relates to an amplifying technique and can be used in signal processing systems where the elimination of noise by the method of averaging a signal over an ensemble of realizations, in particular in medicine, during processing of electroence ™ signals of phonograms and electron diffraction images is required.

 The aim of the invention is to diminish the functionality of the device due to the possibility of averaging the signal over an arbitrary number of CSI implementations.

The fig is a block diagram of the device; FIG. 2 is a diagram of the microprogram control unit i; FIG. 3 is a diagram of an arithmetic logic unit.

A device for analyzing random signals (Fig. 1) contains an analog-to-digital converter (ADC) J, an arithmetic-logic unit 2, a memory unit 3, a second register 4, a microprogram control unit 5, a clock generator 6, a counter 7, the third digital-to-analog converter 8, the input 9 of the command for measuring the analog signal of the average sign 5 clock input 10, counters P 12 and 13, registers 4, 15. and 6, digital-analog. converters 17, 18, demultiplexers 19, 20, multiplexer 21, input 22 commands for the digital signal of the average value,

The program control block (FIG. 2) contains a counter 23, element OR 24, triggers 25-32 ;, elements OR 33, 34, and 35, block 36 of firmware memory.

The arithmetic logic unit (figG contains an averaging node 37, a counter 38, a trigger 39, and elements 40, 4,

The device works in the following way,

The device has four modes of operation: accumulation; LEDs on the Oscilloscope screen; digital output on a computer; analog output on an extended time scale (to a recorder or other slow-acting recorder). Modes are turned on by signals arriving at the inputs of block 5 {Skro- program control,

The following priority has been established for the above operating modes: accumulation mode has the highest priority; computer output mode § analog output mode; indication mode.

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The display mode is turned on for the entire time when the signal inputs of the command code of block 5 of the microprogram T control have no command signal with modes. If one of the specified inputs has a command signal, the device executes the command and then returns to the display mode. the signal is constantly present on the oscilloscope screen regardless of the switching frequency of the dir: imov. There are no signals at the input of the command code of block 5 of firmware etching (CU). A two-bit two-digit code 11 from output 5U is fed to the control inputs of demultiplexers 19, 20 and multiplexer, with the result that the counter outputs are connected to the input of memory block 3 and the input of a digital-to-analog converter 17 for generating an oscilloscope beam deflection signal. The output of register 6 is connected to the input of a digital-to-analog converter (IDT) B, designed to form an oscilloscope's beam vertical signal. The impulse coming from the output of the CU to the recording resolution of register 16, information stored in memory block 3 at the address set in counter 13 is copied to register 16. Then the information input of counter 13 receives a pulse increasing the counter value by unit From the register register 16 information is fed to the input of the DAC 8, forming the ordinate of the next sample. The abscissa of the sample is formed in the DAC 17, to the input of which the code of the sample address is applied. At this point the indication cycle ends with the control unit.

Accumulation mode is turned on if the input of the first digit of the command code of the control unit received a signal from the output of arithmetic logic unit 2, formed from the ready signal of the ADC, if the input signal of the arithmetic logic unit 2 was sent to the device start signal of the next implementation On the device stop signal, the accumulation mode stops, and the installation signal in H) of the device is given, if it is necessary to start accumulation

To the control inputs of the decoders to the multiplexer in the accumulation mode

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code 00 is received. Using a generator pulse 6, applied to the ADC trigger input, another sample of the signal is taken and converted into a binary code, after which the ADC produces a conversion termination signal, which is fed to the input of the arithmetic logic unit, in the arithmetic logic unit the codes are added and the result is divided by the number of implementations. The final result from the arithmetic logic unit 2 is fed to the input of memory block 3. Then the address is incremented in the counter 7, after which the device enters the indication mode, after which the cycle ends and the control unit is again ready to analyze the states of the inputs

If a command to issue a digital signal of an average value has been received at the input of the CU 5, then the information stored in memory block 3 at the address recorded in counter 11 is copied to register 14, then the counter 11 is incremented by a pulse arriving at its input the CU exits, after which the device enters the indication mode, after which the cycle ends and the CU returns to the initial state.

In the analog output mode, the device operates in the same way as in the output mode on a computer.

Firmware control unit 5 operates as follows. At the moment when the state of the counter is 23 000, at the output of the OR element 24 a logical unit j appears which overwrites the state of the triggers 25-28 to the triggers 29-31, taking into account the priority. After the request is received by one of the triggers 29-32, the corresponding trigger 25-28 is cleared to receive the new signal. Firmware memory unit 36 is programmed as follows. At addresses 1000-1111, the program of the Accumulation mode is located, at addresses 1000-10111 is the program of operating mode with a computer, at addresses 100000-1100111 is the program of high-speed mode. analog information at addresses 100000-1000111 - program display mode. The impulse of the request for the indication mode is {n recorded at the last address of the program of each mode.

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In the arithmetic logic unit, the element I 41 analyzes the states of the outputs of the counter 38. A logical unit signal appears at its output when there is a unit in all the bits of the counter 38. This means that the next implementation is processed, and at this moment the accumulation mode stops and unit 2 stops working. To process the next implementation, a pulse must be sent to the device start input. In addition to the code of the number of realizations, the codes from the output of the ADC and the output of the memory block are supplied to the input of the averaging node 37. Node 37 averagedly adds the codes from the outputs of the ADC and the memory block and divides the sum by the code of the number of implementations.

The result is fed to the input of the memory block 3.

Formula of the invention

Claims (2)

I, Random Sigiap Analysis Device. containing an analog-to-digital converter, an arithmetic logic unit, a PGI block, a first register, a counter, a digital-to-analog converter, a microprogram control unit, a clock pulse generator, an anapy-digitizer converter input, is an information input of the device of a clock pulse generator connected with the start of the analog-digital converter, the output of the conversion end of which is connected to the input of the resolution of the analysis of the signal of the arithmetic logic unit, the information output analog A go-to-digital converter is connected to an information input of an arithmetic logic unit whose information output is connected to an information input of a memory block whose output is connected to an information input of a first register whose output is connected to an input of a first digital-analog converter whose output is an output of an average signal device values, the clock input of the firmware control block is also that of the device, the first output of the firmware control block group It is connected to the input of the recording resolution of the memory block, characterized in that, in order to expand function of the device due to the possibility of averaging the signal over an arbitrary number of implementations, two de multiplexers, three counters are entered into it., a multiplexer, three registers, two diffraction analogue converters, the arithmetic logic unit containing a trigger, a counter, two elements And, the averaging node, in the arithmetic-logic block, the first input of the first element I is the resolution of the analysis of the signal of the block, the information input of the averaging node is the information input of the block, the setup inputs in 1 and in the O flip-flop are the start input and the stop input of the device, respectively, the installation input in the O counter is the installation input in the device O., the average accumulated data input of the averaging node is connected to the output of the second register, the inputs of the second And element are connected to the corresponding the bit outputs of the first counter, the trigger setup inputs and the information input of the counter are connected to the output of the second element, And the output from the ratchet is connected to the input of the value of the number of samples of the averaging node,. The output of which is the information output of the arithmetic logic unit, the trigger output is connected to the second input of the first element, the output of which is connected to the input of the first discharge of the command code of the microprogram control unit, the first to the fourth outputs of the first demultiplexer are connected to the counting inputs of the same name counters , exits. which are connected to the corresponding inputs of the multiplexer, the output of which is connected to the address inputs of the lower bits of the memory block, the output of which is connected to the information inputs from the second to the fourth registers, the output of the third register is the output of the digital signal of the average value of the device, the fourth output th counter is connected to the input of the second a digital-to-analog converter, the output of which is the output of an analog signal of a device's ordinate, the output of a fourth register is connected to the input of a third digital-analog converter, the output of which is an output of an analog signal of an absolute signal from a device, from the first to 4eTBepTbd you 5 0 O 5 0 236 the second demultiplexer moves are connected to the write resolution of the same name registers, the analog command output signal of the average value and the digital output signal of the average signal of the microprogram control unit are correspondingly the same as the second and sixth outputs of the group first and second bit information inputs of the first demultiplexer, with control inputs of the first and second demultiplexes s and a multiplexer, to the address input MSB block of memory to the second data input of the demultiplexer. 2. The device according to claim. 1, that the microprogram control block contains a counter, four OR elements, eight flip-flops, a microprogram memory block, the counter input being the clock input of the block, the first, second and third outputs. the counter bits are connected to the same inputs of the first element OR and the same bits of the memory block of the firmware; the installation input to the first one trigger is the input to the first discharge of the command code of the unit, the installation input to the second trigger is the input to the second discharge Yes, the block command code, the setup input in 1 of the third trigger is the input to the third bit of the block command code, the outputs from the first to the fourth flip-flops are connected to the installation inputs in 1 from the fifth to the eighth triggers, respectively, the outputs from the fifth to the eighth flip-flops are connected to the installation inputs in O from the first to the fourth flip-flops, respectively, the write enable inputs from the fifth to the eighth flip-flops are connected to the output of the first OR element, the first inputs from the second to the fourth OR elements are connected to the fifth trigger output, and the second th inputs of the second to fourth OR element and set input of G fifth latch connected to the address output unit floor micro memory MHKponporpai iM, A third inputs of the third and fourth members are connected to IL vghodom sixth trigger. 713271 the fourth input of the fourth element OR is connected to the output of the seventh trigger, the outputs from the second to the fourth elements OR are connected to the installation inputs to O from the sixth to the eighth flip-flops, respectively, the outputs from the fifth to the eighth flip-flops are connected The fourth to seventh addresses of the microprogram memory unit are, respectively, the first through the sixth outputs of the micro-operations field of the microprogram memory unit group, respectively, the first to the sixth outputs of the block. Editor M. Bandura Compiled by V. Orlov Tehred I.Popovkch Proofreader A.T sko Order 3391/46 Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, 4/5 Production and printing company, Uzhgorod, st. Project, 4