SU1361564A1 - Addressing device - Google Patents

Abstract

The invention relates to computing. The purpose of the invention is to expand the scope of use by increasing the amount of plug-in RAM. The device contains K 1 microcomputers, 2 processor, non-switchable memory block 3, memory blocks 4, k p ptopop 6, address decoder 7, register 8, line negotiators, and high-order address drivers. All blocks 4 of memory have the same addresses for processor 2. Selection of a specific block of memory 4 is carried out by entering the number of the memory page into register 8. Tables 1, 3, or 4. Q e (L z about SP about:

Description

The invention relates to computing.

The purpose of the invention is to expand the scope by increasing the amount of connected RAM.

Figo is a block diagram of the device for addressing; Fig. 2 is a block diagram of the former high-order address bits; FIG. 3 shows the distribution of memory addresses between memory blocks.

The device contains (figure 1) common highway 1. microcomputer, central processor 2, non-switchable memory block 3, memory blocks 4, trunk adapters 5, switch 6, decoder 7, register 8, encoder 9, and shapers of the higher-order address bits.

The imaging unit 10 (figure 2) contains two elements And 11 and 12.

The device works as follows.

Processor 2 has access via trunk 1 to block 3 of non-switchable memory, which is configured so that the upper RADES of the RADS 16 and RAD 17 addresses do not affect its operation. Unit 3 occupies the physical addresses of the address space of the computer, as shown in FIG. Memory block 4 contains three modules that are configured for a specific code of additional address bits RAD 16 and RAD 17 (codes 01, 10 and P). Code 00 in the device is not used by any module of block A and is intended to turn off all blocks 4 of this trunk.

The activation of a specific memory block 4 is provided by entering into the register 8 the number of the active memory page. To register 8, processor 2 has access to both write and: read through switch 6. Address decoder 7 is set to free

address from the external device address zone.

Depending on the value of the active page number entered in register 8, one of memory blocks 4 is programmatically accessible to processor 2.

The activation of a specific block 4 occurs according to the table.

Claims (1)

Invention Formula A device for addressing, containing the address decoder, register, the switch, the memory block, the address decoder input is connected to the device address input bits, the address decoder output is connected to the register sample input, the output of which is The information input-output of which is connected to the input-output of the bits of this device, the output of the switch is connected to the information input of the register, characterized in that, in order to expand the scope by increasing the amount of connected RAM, he entered k-blocks memory, encoder, (K + 1) shapers of higher-order address bits, with the register output connected to the input of the encoder, the first input-output of which is connected to the first inputs from the first by (K + 1) -th former shapers address bits, from the second to (K + 2) -th outputs of the encoder are connected to the second inputs from the first to (K + 1) -th shapers of the higher-order address bits, respectively, the information inputs-outputs and the lower bits of the address input of the C-th memory block (, ..., K + 1) are connected to the data input-output bits and the address input bits the devices, the C-th outputs of the high-order address bit are connected to the high-order bits of the address input of the C th memory block. Table continuation Figg 8-8 WU Zone JoHff non-swapable RAM 7M Zone nepBKfw- RAM RAM About page page n-page Editor V. Bugrenkova Compiled by A. Trunov Tehred A. Kravchuk Order 6292/49 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 3 Proofreader N.Korol