SU1460740A1 - Memory device - Google Patents

Abstract

The invention relates to computing, in particular, to remembering devices, and may find application in microprocessor technology. The aim of the invention is to improve the speed of the device. The goal is achieved by the fact that the device contains a register 12, an inverter 13, the first and second groups of elements And 16, 17, the first and second groups of key elements 14, 15 s

Description

one

The invention relates to computing, in particular, to storage devices, and can be used in mini-computers and micro-computers and microprocessors.

The purpose of the invention is to increase the speed of the device.

The drawing shows a functional diagram of the storage device.

The device contains a matrix drive 1, consisting of memory blocks 2, the first decoder 3, the second decoder / t, two groups of registers 5, the write-read input 6, information input-output 7, address inputs 8 of the first group (low-order bits) and of the second group 9 (high-order bits), direct access permission input 10, logical unit 11 input, register 12, inverter 13, key elements

14 of the first group, key elements

15 second group, elements And 16 and 17. Drive 1 is divided into two matrices. The first matrix is a basic drive (in the drawing

the first and second rows of accumulator 1), and the second matrix is the information storage (only the last row of the matrix is conventionally shown in the drawing).

Memory blocks 2 are semiconductor memory blocks having two sample inputs. Decoder 3 -, the usual potential decoder. The decoder 4 has, in addition to the information (address) inputs, also a control input (for example, K55ID4, K55ID7 chips). At one of the outputs, its decryption signal appears only when a signal is applied to its control input, and the duration of the output signal is equal to the duration of the signal at the control input of the decoder. Registers 5 and 12 - ordinary

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five

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five

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five

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registers, for example, K555TM9. Elements 14 and 15 are repeaters with three-stable outputs. Chips K555LP8, K580VA8.6, K585AP16 can be used. An input 11 of a logic unit is an input connected to the output of an inverter with a grounded input; therefore, it always (with power turned on) contains a signal of a logical unit. This signal can be formed inside a storage device (memory) and is not activated externally. Inputs 6 and 8-10, as well as input-output 7, are connected to the corresponding processor outputs. In addition, input 6, input / output 7, and inputs 8 and 9 of the storage device are connected to the direct memory access channel (PDP channel).

The memory has two modes of operation - the main and direct access mode.

Consider the main mode of operation. Since the memory size of the memory device significantly exceeds the volume of the directly addressable memory, equal to 2 memory cells, where n is the size of the address bus of the processor, then for the processor to work, it is necessary to create a working page equal in size to the directly addressable memory and containing 2 memory blocks. The page is organized in such a way that from each row of accumulator 1 there is only one block 2 of memory (any, but one that is needed at this stage of the calculation). The working page is programmed using the registers 5 and the decoder 3. Since the information inputs of the registers 5 are connected to the information input-output 7 of the device, and through the second decoder 4 their inputs are connected to the address inputs 8 and 9 of the device, these registers are software accessible.

1460740

In the first matrix, the resolving potential from the output of the register 5 goes directly to the corresponding memory block 2, and to the second through element 14, which is open by a high potential coming from the output of the inverter 13 to its sample input, since during the main memory mode, the input is input 10 direct access from the processor is low potential. The elements 15 are closed. Blocks 2 of memory, to the second input of the sample of which enters the rae

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in the case of the required direct memory access, the direct access controller supplies the processor with a capture signal, in response to which the processor supplies the input potential memory 10 to the high potential of the direct access and transfers its output data buses to the high-impedance state write-read and address. The memory goes into direct access mode. The inverted direct access enable signal comes from the inverter 13 to the inputs of the And 17 elements of all

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decisive potential with the corresponding 15 lines of the base memory in the form of prohibiting SIGMN S uon.m “. -. "H

register 5, we will call semi-selected.

. During program execution, the processor places different codes on the address bus, the first address group is fed to the address inputs of all 2 memory blocks, and the second group to the inputs of the first decoder 3. One of the decoder outputs is energized, and this signal is sent to one of the lines of the basic or information memory. In the basic accumulator, this signal is fed to one input of the corresponding element AND 17, to the other input is supplied the resolving potential from the output of the inverter 13. From the output of the element AND 17, the resolution is fed to the first inputs of the sample and all the blocks 2 lines. In the information

the first one, all elements of AND 17 are closed and all lines of the base memory are blocked by the first inputs of a sample of 2 memory blocks. At the same time, in the 2P lines of the information storage device, the outputs of the elements 14 (transferred to the high-impedance state) are closed by a low potential arriving at their sample input from the output of the inverter 13. One 25 of the inputs 16 and 16 in each of the lines of the information storage has a high potential direct access from input 10, to the other inputs of elements AND 16, the corresponding 30 outputs of the additional register 12 are entered. This register, like the registers 5, is program-accessible. In it, as well as in registers 5, the processor writes in a programmatic way

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the drive output of the first decoder 3 3., the code of that line of information memory is fed to the ixpn zgtok ots ,, i /,

enters the input of the element 14 of the corresponding line, and from its output - to the first inputs of the sample of all blocks of 5 memories of its own line.

Now, in the corresponding unit of accumulator 1, which is accessed, only one memory unit 2, namely the half-selected one, becomes selected and the reference is made only to it. If the processor finishes processing the information in the selected configuration of the working page, it can form a new working page with other blocks of 2 memory. In this mode of memory, the processor can access any memory block 2, all the memory blocks 2 within the same line occupy the same part of the address space, i.e. are like twins.

Addressing memory cells in a working page increases from top to bottom, i.e. the working memory page is vertically addressed.

which in the next cycle of direct access is provided to the channel of direct access. Writing information to the register 12

40 is produced by the processor prior to issuing a direct access enable signal to the input 10 of the memory. The register 12 is written with the unitary code of the line number, as a result of which only one of its VBGKHOD

45 is set to one; This output is entered into the AND 16 element of one of the lines of the information memory. The resolving potential from the output of this element enters the input of the element 15 and opens its outputs. At the same time, the signal of the logical unit from the input 11 of the logical unit through the element 15 of this row of accumulator 1 enters the first inputs 55 of the sample of memory blocks 2 and makes them half-selected.

Thus, in the mode of direct access to the memory, all lines of the base memory and lines except one are blocked.

in the case of the required direct memory access, the direct access controller supplies the processor with a capture signal, in response to which the processor supplies the input potential memory 10 to the high potential of the direct access and transfers its output data buses to the high-impedance state write-read and address. The memory goes into direct access mode. The inverted direct access enable signal comes from the inverter 13 to the inputs of the And 17 elements of all

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lines of the base memory in the form of prohibiting 15 lines of the base memory in the form of prohibiting .g -. "H

the first one, all elements of AND 17 are closed and all lines of the base memory are blocked by the first inputs of a sample of 2 memory blocks. At the same time, in the 2P lines of the information storage device, the output of elements 14 (transferred to the high-impedance state) is closed by a low potential arriving at their sample input from the output of the inverter 13. One 25 of the inputs AND 16 in each of the lines of the information storage receives a high potential of resolution direct access from input 10, to the other inputs of elements AND 16, the corresponding 30 outputs of the additional register 12 are entered. This register, like the registers 5, is program-accessible. In it, as well as in registers 5, the processor writes in a programmatic way

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3., the code of that line of information memory

3., the code of that line of information memory

which in the next cycle of direct access is provided to the channel of direct access. Writing information to the register 12

0 is produced by the processor before issuing a direct access enable signal to the input 10 of the memory. The register 12 is written with the unitary code of the line number, as a result of which only one of its VBGKHOD

5 is set to one; This output is entered into the AND 16 element of one of the lines of the information storage device. The resolving potential from the output of this element enters the input of the sample of element 15 and opens its outputs. At the same time, the signal of the logical unit from the input 11 of the logical unit through the element 15 of this row of the accumulator 1 enters the first inputs of the Dy sample of memory blocks 2 and makes them half-selected.

Thus, in the mode of direct access to the memory, all lines of the base memory and lines except one are blocked.

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information storage, and only one line of information storage (pre-programmed) remains available for operation. The forward controller (not shown) directs the address of the exchange to the address inputs 8 and 9, then loads quickly (the direct access device sends information to the information input / output 7 of the memory) or downloads this line of the accumulator 1. My access sends the corresponding signals to the input 6 of the memory. A direct access device is provided with a large memory and the change of information in the row is very fast,

In the direct access mode, the memory addressing in the row is horizontal, i.e. the first memory block 2 has a starting address O, and the last memory block has an ending address 2 -1. During the input (or output) of information to this line (or from it), the addresses at address inputs 8 and 9 change, while the outputs of the first decoder 3 sequentially excite one of the outputs and, through element 15, feed the second input of the corresponding sample; a block of 2 lines of memory, as a result of which only this block of 2 memory becomes cut out and reference is made only to it. After the transfer of the information is completed, the forward-access controller informs the processor of this, the last removes the high potential of direct access resolution from the 10-memory input, and the latter goes into the normal mode of operation.

Claims (1)

Invention Formula A storage device containing a matrix storage device, two decoders, two groups of registers, informational inputs of which are connected to the information storage input-output of the matrix storage and which are information input-output of the device, the input storage entry-readout of the matrix storage, address recording the inputs of the matrix accumulator are the address inputs of the first device group, the inputs of the first decoder are five 0 g 0 25 0 The address inputs of the second group of the device, the inputs of the second decoder are connected respectively to the inputs of the first decoder, the address inputs and the write-read input of the matrix drive, and the outputs, except for the last, second decoder, are connected to the sample inputs of the corresponding registers of the first and second groups, the outputs of the registers of the first group connected to the corresponding inputs of the column selection of the first group of matrix storage, for example, in order to improve the speed of the device, it contains The register, inverter, two groups of I elements, two groups of key elements, the information input of the register connected to the information input / output of the matrix accumulator, and the sample input - with the last output, the second decoder input, the input of the inverter and connected to the first inputs of the elements of the first group, and the output of the inverter is connected to the inputs of a sample of key elements of the first group and to the first inputs of the elements of the second group, the outputs of which are connected to the corresponding inputs of the orcs of the row of the first group of the matrix accumulator, and the second inputs - with the corresponding outputs of the first 35 decoder and with the corresponding inputs, except for the last, key elements of the second group, the last inputs of which are connected to the potential bus of the logical unit of the device The second group is connected to the outputs of the corresponding elements And the first group, the second inputs of which are connected to the corresponding register outputs, the outputs of the registers of the second group are connected to the corresponding inputs, cr ome last, the corresponding cells of the first elements of the group, the last inputs of which are connected to the corresponding outputs of the first decoder, the outputs of the key elements of the first group are connected to. the corresponding outputs of the corresponding key elements of the second group and with the inputs of the sample of the corresponding lines and columns of the second group of the matrix accumulator. 0 0 45