SU1644150A1 - Device for interfacing two computers - Google Patents

Abstract

The concept relates to computer technology, is intended for interfacing two computers that have a mainline parallel interface, and can be used to test and debug storage and external devices of a slave computer, as well as for machine-to-machine information exchange. The aim of the invention is to expand the functionality by providing an operational setting of the host computer to the direct access mode and a given address area of the slave computer while quickly and independently changing the boundaries and sizes of the addressable area of the master and slave computers. The device contains a bus driver unit, a register of significant bits, a control signal switching unit, a command decryption unit, an address switching unit, a mode decoder, a bit address comparison unit, an address decoder, two address registers. 8 il. (L

Description

The invention relates to the field of computer technology, is intended for interfacing two computers having a mainline parallel interface, and can be used for testing and debugging storage and external devices of a slave computer, as well as for computer-to-machine information exchange.

The purpose of the invention is to expand the functionality by ensuring the operational setting of the host computer to the mode of direct access to the specified address area of the slave computer while quickly and independently changing the boundaries and sizes of the area.

addressable space (window) of the master and slave computers.

FIG. 1 shows a block diagram of the device; in fig. 2 is a block diagram of a one-bit address comparison block; in fig. 3 - structuring the register of significant bits; in fig. 4 is a block diagram of an address switching unit; in fig. 5 is a structural diagram of a mode decoder; in fig. 6 is a block diagram of a control signal switching unit; in fig. 7 is a block diagram of the bus driver circuit; in fig. 8 - illustrations of work

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routines for transferring information from the host computer to the slave computer and back. . A pairing device, designed to control the memory of the slave computer, enters the system, which contains (Fig. 1) the host computer 1t containing memory 2, processor 3, control line 4 and information highway 5V forming the - | schyu highway 6; a slave computing machine (computer) 7, which contains memory 8, a processor 9, connected to a common line 10, which consists of a control line 11 and an information line 1 2.

The interface device 13 comprises an input-output 14, an input-output 15, a bus driver 16 block, a command decryption block 17, an address comparison block 18, a register of 19 significant bits, the first address register 20, a second address register 21, a block 22 switching control signals, address switching unit 23, a decoder 24 modes, an address decoder 25, input-output 26, input-output 27

Block 18 of the bitwise address comparison (Fig. 2) contains the AND-NE elements 28 and 29, the AND-OR-NOT 30 element for one bit. Similarly, a circuit is constructed for all sixteen bits. FIG. 2, inputs 31, 32 and block output 33 are also indicated.

The register of 19 significant bits contains (fig. 3) sixteen flip-flops 34-49 (36-47 not shown) (the number of flip-flops depends on the number of bits of the address of the master and slave computers), input 50 and output 51.

The address switching unit 23 (FIG. 4) contains the AND-HE elements 52 and 53, the AND-OR-HE element 54, the bus driver 55. The unit contains four bus driver, inputs 56-60, input and output 61.

The decoder mode 24 (Fig. 5) contains the elements AND-NOT 62-67 inputs 68 and 69, output 70, input 71.

The control signal switching unit 22 (FIG. 6) contains input-output 72, output 73, input-output 74, outputs 75-77, bus drivers 78- 81, AND-NE elements 82-86.

The block 16 of tire formers (Fig. 7) contains the input-output 87, you0

five

0

stroke 88, inputs 89 and 90, the bus drivers 91-94, element AND-NOT 95.

The command decryption block 17 is a commercially available IC K1801VP1-33 KO.348.570-03 TU, manufactured using n-channel MOS technology and in 42 output ceramic type 429.42-5, operating in the mode of the parallel input-output interface controller.

The second address register 21 is a commercially available IC K1801BP1-34. ECO.348-570-03 TU, manufactured & No. in the n-channel MOP technology in a 42 pin ceramic housing type 429.42-5.

The work of the device is illustrated by the subroutines window 1, window 2, which allow to transfer information from the window.

0

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0

0

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on and

in the memory card of the leading computer of 1 c.

five

the window located in the memory card of the slave computer 7 and back using the buffer area in the memory card of the host computer 1. The window memory area in the memory card of the host computer 1 should be turned off.

Define the input parameters for the subroutines window 1, window 2 (Fig. 8):

address of the first address register

20 167742;

address of the second address register

21-167744;

address of the lower border of the window in the computer memory card 1 20000;

the address of the upper boundary of the window in the computer memory card 1 37776;

the address of the lower boundary of the buffer region in the computer memory card 60000;

the address of the lower border of the window in the computer memory card 7 120000;

The device works as follows.

As a result of the operation of one of the subroutines window 1 or window 2 of the host computer 1, the lower boundary of the window in the memory card of the host computer 1 is written into the first address register 20, then the upper edge of the window in the memory card of the master computer 1 is written to the second address register 21. S to the device 13, the upper and lower bounds of the window are compared in block 18 of the bit address comparison, and the result of the comparison is written to the register of 19 significant bits. In the second register, 21 addresses write the bottom,

window

I’m on my computer 7 in the Vedogran memory card.

After writing this information into registers, block 18 is a bit

, address comparisons and address decoder 25 analyze the addresses of the cells that are addressed to

addressable space of the host computer window 1.

The host computer 1 sets the slave computer 7 to the direct access mode. MOV # NG01, RO MOV # VG01, R1 MOV # NG01, R2

MOV # NG02, R3

entering input parameters into general registers

Using the subroutines window 1 and window 2, you can quickly change the boundaries and sizes of the window area of the master and slave computers by entering the input parameters into general registers.

Window MOV RO, RA1 MOV R1, RA2 MOV R3, RA3

LOOR1: MOV (R2) + (RO) +; transfer of information from the window in the memory card of the host computer CMPRO, R1: 3BM 1 to the window area

in the slave computer memory card 7 BEQ LOOP 1 RTS PC

The first command records the address of the lower window border in the memory card of the host computer 1 in the first register

20address. The second command records the address of the upper border of the window in the memory card of the host computer 1 in the second register 21 of the address. When writing the address of the upper boundary of the window in the memory card of the host computer 1 in the second register

21 addresses are a one-by-one comparison of the addresses of the upper and lower bounds of the window in the memory card of the master

The computer 1 in block 18 of the one by one address comparison and the result of the one by one comparison is recorded in a register of 19 significant bits.

The next subroutine command window 1 records the address of the lower window border in the memory card of the slave computer 7 into the second register of the address 21. If you are accessing the slave computer window area 7, then with output 1644150

five

0

five

Yes 76 of address decoder 25 receives an active signal to the input of control switching unit 22, which opens and passes the response signal (CIP) from the slave computer 7 to the host computer 1 by this signal. The next two commands verify the output from the window area to

Q master memory card 1.

The address switching unit 23 passes a bit of information to the input-output 27 of the device 13, either from the 16-tire driver unit or from

5 of the second register 21 addresses depending on the code that is stored in the register of 19 significant bits, provided that the signal Output is set by the CPU 3 leading

0 computer 1 (Fig. 1) is inactive. If the central processor 3 of the host computer 1 sets the output to active state, then the address switching unit 23 will pass information from the input-output 15 of the device 13 through the block of 16 bus drivers, regardless of the contents of the register 19 significant bits. Thus, the proposed device transmits information (data) from the input-output 15 of the device to the input-output 27 of the device. In this case, the decoder 24 of the mode issues signals to the address switching unit 23, to the bus drivers unit 16 and to the control signals switching unit 22, thereby setting the transceivers in these units to the following states: in the bus drivers block 16 to transmit information from the input output 5 to the address switching unit 23 and from input-output 61 of this block to input-output 27 of the device 1 3.

By transferring the contents of the cells of the buffer area (60000-77776) with the lower limit of 60000 to the window area in the memory card of the host computer 1 through device 13, the contents of the cells of the buffer area are transferred to

0 mode of direct access to the slave computer memory 7.

Subroutine window 2 of transferring the contents of the window area in the memory card of the slave computer 7 to the buffer area in the memory card of the computer 1, using the window area in the memory card of the host computer 1, looks similarly.

Window MOV RO, RA1

MOV R1, RA2

MOV R3, RA3

LOOP2: MOV (RO) +, (R2) +

CMP RO, R1

BEQ LOOP2

 Res pc

When the signal level is active Output that is generated in control line 4, when the third subroutine operator window 2 is executed, the mode decoder 24 produces control signals that switch the address switching unit 23 and the bus driver unit 16 so that the signals go from output 27 to input-output 15, entering input-output 61 of address switching unit 23, exit from output 59 of this block and arriving at input 90 of block 16 of bus drivers, then from input-output 87 of this block go to input- output 15 of the device 13. So the data is organized in the manner from reading the memory area of the slave computer window 7 and writing to the buffer area in the memory of the master computer 1.

Bitwise address matching unit 18 (Fig. 2) operates as follows: bits 31 are supplied to input 31, which define the lower boundary of the window in the memory card of the host computer 1, and address bits of the host computer 1 are supplied at input 32. provides a one-to-one comparison of the codes arriving at its inputs and outputting at output 33 a code determining the result of a one-by-one comparison.

Register 19 significant bits (Fig. 3) works as follows. From output 33 of block 18, a code is received that determines a one-time comparison result in the category where there is a negative one-time comparison result — logical 1 triggers are written into the triggers of this and all the least significant bits, and bitwise positive comparison - the logical O is recorded. The code generated in this way is fed from OUT and 51 to the input of address decoder 25 and stored in triggers 34-49. Input 50 provides signals that control the process of recording and reading information.

The address switching unit 23 (Fig. 4 allows, depending on the code that is stored in the register 19 of the significant bits), to obtain at the output the code

according to the following logic - if the signal Output in the host computer 1 is set to inactive, then depending on the register contents, 19 significant bits in this bit at the output of address switching unit 23 receive either the value of logical signals going to input-output 15 without change, or the value of the logical signal for a given bit, recorded in the second address register 22, i.e. modified signal value for a particular bit.

If the output signal is set to the active state, then regardless of the contents of the register 19 significant bits in this bit, the output of the circuit receives the inverse value of the signals from the input-output 15 of the device 13.

All bits of this block work in the same way. Input 56 is connected to input 88 (Fig. 1) of block 16 of bus drivers, this input receives signals from input-output 15 of device 13. Input 57 is connected to the output of the second address register 21, this input receives bits of the lower boundary of the slave window Computer 7

Input 51 is connected to the register output of 19 significant bits, this input receives information about the result of comparing the lower and upper boundaries of the window of the master computer 1. Input 58 is connected to input 89 of the bus driver unit 16, this input receives a signal Output from block output 68 22 switching control signals.

The decoder 24 mode (Fig. 5) works as follows. In the absence of a signal (logical O) at the input 69 of the decoder 24, the circuit outputs signals at the outputs 70 and 60, under the action of which the input-output 61 of the address switching unit 23 and the input-output 74 of the control switching block 22 are set to a high impedance state .

With the active level of the signal, which arrives at the input 69 of the decoder 24, and with the active level of the signal at the input 68, the circuit produces signals that transfer the address switching unit 23 to the information transfer mode from input-output 27 via the block 16 bus drivers to the input - exit 15.

to

15

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At the passive level of the signal arriving at the input 68 of the decoder 24, the circuit generates signals at the output 60, under the action of which the address switching unit 23 is set to the following information transfer direction: from input-output 15 through block 16 of bus drivers to input-output 27.

With a passive logic level, the signal at input 69 of the decoder 24, regardless of other signals that arrive at the inputs of the decoder, it sets the control switching unit 22 to the following direction of information transfer: from input-output 14 to input-output 26.

The control signal switching unit 22 (Fig. 6) operates as follows: the control signals from the host computer 1 enter input-output 72 and, passing through the bus driver 78-80, arrive at input-vm - stroke 74. The control signals TPR.SBROS received from the input-output 26 of the slave computer 2 to the input-output 74 of the block 22 switching control signals and, pass through the bus driver 81, go through the input-output 72 to the input-output 14 and into the host computer 1.

The response signal SIP from the host computer 7 is fed to the input 75 of the block 22 switching control signals. The IS-NE element 82 passes this signal further to the delay line, consisting of elements 83, 84 and 86, only if the signal arriving at input 76 is active, i.e. the CIP response signal will pass through the AND-NE 75 element if there is an appeal to the window of the memory area of the host computer. Element AND-NOT 85 will miss the CIP response signal only if at input 77 a signal that goes

20

25

thirty

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ten

de 89. another signal is installed, bus drivers 91-94 are set to the following information transfer direction: signals from input-output 27 of slave computer 7, passed through address switching unit 23, output 59 of this block is fed to input 90 of block 16 bus drivers and then, having passed through the mud shapers 91-94, are fed to the input-output 87 and then to the input-output 15 of the device 13.

Claims (1)

Invention Formula A device for containing two computers containing a control switching unit, a first address register, an address switching unit, an address decoder, the first and second groups of information inputs / outputs of the control switching unit forming a device I / O group for connecting to the control the tires of the first and second computers, respectively, the group of information inputs / outputs of the address switching unit forms the group of inputs and outputs of the device for connecting the second computer to the information bus, the first information The input and output of the switching unit of control signals are the input and output of the device for connecting a second computer to the control bus, characterized in that, in order to expand the functionality by providing an on-line setting of the host computer for direct access to the specified address area slave computer with operational and independent changes in the boundaries and sizes of the addressable area of the master and slave computers, a block is entered into the device r.J Cl-din Oh, and, - I I rii,, 7 "h - - from the decoder block 17 of the rope (Fig. 1) of the tire formers, the register will be active. Block 16 tire drivers (Fig. 7) works as follows. Signals from input-output 15 of device 13 (Fig. 1) come to input-output 87 of the block of bus formers, pass through elements 91-94 and arrive at output 88. This happens if the input 89 of block 16 of bus forts 50 chapters, a command decryption unit, a mode decoder, a second address register, a one-by-one address comparison unit, the group of information inputs / outputs of the bus driver unit forms the device input-output group for connecting the first computer to the information bus, the first information input of the demister receives the corresponding 55 The mode encoder is the input of a signaling signal that sets bus drivers to the information transfer direction described above. If, on the other hand, for connecting a second computer to the control bus, the second information output of the switching unit 0 ten de 89. another signal is installed, bus drivers 91-94 are set to the following information transfer direction: signals from input-output 27 of slave computer 7, passed through address switching unit 23, output 59 of this block is fed to input 90 of block 16 bus drivers and then, having passed through the mud shapers 91-94, are fed to the input-output 87 and then to the input-output 15 of the device 13. Invention Formula 0 five 0 five 0 A device for containing two computers containing a control signal switching unit, a first address register, an address switching unit, an address decoder, the first and second groups of information inputs / outputs of the control switching unit form a device I / O group for connecting to control buses the first and second computers, respectively, the group of information inputs / outputs of the address switching unit forms the group of inputs and outputs of the device for connecting the second computer to the information bus, the first information The input and output of the switching unit of control signals are the input and output of the device for connecting a second computer to the control bus, characterized in that, in order to expand the functionality by providing an on-line setting of the host computer for direct access to the specified address area slave computer with operational and independent changes in the boundaries and sizes of the addressable area of the master and slave computers, a block is entered into the device tire formers, register of tire formers, register of chapters, a command decryption unit, a mode decoder, a second address register, a one-bit address comparison unit, the group of information inputs / outputs of the bus driver unit forms the device input-output group for connecting the first computer to the information bus, the first information input of the mode decoder is the input of the device for connecting the second computer to the control bus; the second information output of the control signal switching unit is connected to the control inputs of the bus driver unit address switching with the second information input of the mode decoder, the output group of which is connected to the group of control inputs of the address switching unit, the information output group of which is connected to the group of information inputs of the bus driver unit, the group of information outputs of which is connected to the first groups information inputs of the block of comparison of the address, address switching unit, and command decryption unit, with groups of information inputs of the first and second address registers, the second group The Upp of the information inputs of the command decryption unit is connected to the second group of information inputs / outputs of the switching unit of control signals, the control input of which is connected to the output of the mode decoder, the third information input of which is connected to the second information input of the switching unit of control signals and the first output of the command decryption unit, the second output of which is connected to the first permitting input of the control switching unit, the second permitting input of which is connected to the decryption output The address of the address, the first group of information inputs of which is connected to the group of information inputs of the register of significant bits and the group of outputs of the block of comparison of the address, the second group of information inputs of which are connected to the group of information outputs of the first address register, the group of outputs of the decryption block of the first the address register, the second address register, and the group of information inputs of the register of significant bits, the group of information outputs. which is connected to the second group of information inputs of the address decoder and to the second group of information inputs of the address switching unit a third group of information inputs of which are connected to the group of information outputs of the second address register. h " fe Lj one four l i ft S3 SO FIG. 61 about in r} vD FIG. 7