SU1352646A1 - A-d converter - Google Patents

Abstract

The invention relates to an information measurement technology and can be used in digital voltmeters, ohmmeters and combined instruments. The invention makes it possible to increase the accuracy and simplify the converter. This is achieved by the fact that in the converter containing the keys 2,3,7, resistors 4,5,6, integrator 9, source 1 of the reference voltage, elements AND 14,15,12,13,22, pulse counters 16,19, 20, triggers 21,23, comparator 11, entered comparator 10 and display unit 17. 2 Il. SL C fie.1

Description

The invention relates to an infrared, measuring and measuring technique and can be used in digital volt-. ohm meters and combined instruments.

The purpose of the invention is to improve the accuracy and simplification of the converter.

Figure 1 shows the functional diagram of the device; figure 2 - .time diagrams of the device.

The device contains a source of 1 reference voltage, which via keys 2,3, resistors 4,5,6 and key 7

Here, numbers 33-56 indicate the moments of the re-switching of the keys 2, 3.7 and the straight line marked

f Ug is the zero offset in voltage at the first comparator 10.

The device operation algorithm is set by counters 19.20 and trigger 23. Counters 19.20 count pulses.

10 seconds of the generator 18. The trigger 23 determines the duration of the conversion cycle, controlled by pulses from the code of the counter 20 and element 22 ,. the inputs of which receive pulses from

connected to the ADC input bus 8, total 15 counter 20 and generator 18. Trigger

point of resistors through the integrator

9 connected to the inputs of the comparators

10 and 11, the output of the comparator 10 is connected to the second input element And 12,

the first input of which is connected to the second 20 DUT, the pulses of a specific eye input element I 13, which is a combination of duration, are allocated. The fronts of these parator pulses 11, through elements 14 and 15, determine the beginning of the discharge, the pulse counter 16 is connected to the integrator (Fig. 2, plot 27). display unit 17, element output With an appropriate choice of the coefficient I 14 is connected to the control input 25 of the dividing counter of the counter 20 into its key 3, the second input of the element 15 and the output will generate pulses

moment setters

connected to the first input element And 12, the second input of the counter 16 pulses connected to the output element And 13,

the integrator 9, the current generated by the measured voltage U ,. Trigger 23

the output of the generator 18 pulses connects 30 forms intervals defining

 yen with the corresponding inputs of the elements And 12 and 13 and the counter input .19 pulses, the output of the counter 19 is connected t by the input of the counter 20 pulses and the first input of the trigger 21, the second input of which is connected to the output of the element 12, and the outputs to the inputs of the key 2 and element 13, the inputs of element 22 are connected to the outputs of generator 18, counter 20 and the first input of trigger 23, the second input of which is connected to the output of element 22 and 22, the output of trigger 23 is connected to the control input of key 7 and the second input of element 14 .

The time diagrams illustrating the operation of the device are shown: on the graph 24 - the law of change in the conductivity of the key 7; 25 - the law of change in the conductivity of the key 2j 26 - the law of change in the conductivity of the key 3; 27 is the law of voltage variation at the output of the integrator; 28 is the law of filling the counter 16j 29 — on a larger scale plot A of graph 27, where 30 is the law of voltage variation at the output of the integrator 9} 31 is the bias voltage of the comparator zero zero 10; 32 - pulses at the output of the generator 18.

Here, numbers 33-56 indicate the moments of the re-switching of the keys 2, 3.7 and the straight line marked

Ug is the zero offset in voltage at the first comparator 10.

The device operation algorithm is set by counters 19.20 and trigger 23. Counters 19.20 count pulses.

from generator 18. Trigger 23 determines the duration of the conversion cycle, controlled by pulses from the code of counter 20 and element 22 ,. the inputs of which receive pulses from

23. Performs key management 7.

When choosing the frequency of the generator 8 and the corresponding dividing factors of the counter 19 at its output of the integrator 9, the current generated by the measured voltage U ,. Trigger 23

one measuring cycle consisting of an integrating cycle 33-53 and an accompanying 53-57 cycle.

In the interval of integration of the signal-3g scrap from the output of the trigger 23, the key 7 is closed, in the preparation interval it is open (figure 2, graph 24).

At the initial moment of time, the input of the integrator 9 from input 8 through the closed switch 7 and the resistor 6 supplies a current, the value of which with an ideal switch is determined by the ratio of the measured voltage U to the resistance value of the resistor 6. The output voltage of the integrator 9 starts linearly increase (figure 2, graph 27). The voltage increment at the output of the integrator 9 over the time interval 34-33 will be

and.

P

PL

it

R, .C

about,

(one)

where lsd is the elementary time interval equal to the voltage period at the output of the generator 18, and the number of elementary intervals during the time interval 34-33;

R.135 is the resistance value of the resistor of 6; C is the capacitance value of the capacitor in the integrator 9. At time 33, after some time after the start of the integration, switch 2 closes and the input of integrator 9 through the switch 2 and the resistor 4 is supplied with the discharging current from source 2. The switch 2 is controlled by trigger 21, receiving pulses of the beginning of a discharge, with counters 19. The law of change in the conductivity of key 2 is shown in graph 25 of FIG. 2.

For simplicity, let us assume that the magnitude of the discharge current doubles the charge current from input 8 at Ux equal to the voltage of source 1.. Under this condition

R. 0,5 R

6

(2)

Where

four

resistance value of resistor 4.

The voltage at the output of the integrator 9 decreases linearly. At the moment when the voltage at the output of the integrator 9 becomes equal to the zero offset of the comparator 10, from its output to the element 12 comes the enabling signal, to the first input of the element 12 it receives pulses from the output of the generator 18, having a period utj ,. The front of the first of these pulses, which passed through the element 12, after the appearance of the resolution at its second input, overturns the trigger 21, opens the key 2 and turns off the discharging current. Thus, the device works so that the interval 33-35 is formed from integer number of elementary intervals db (see chart 27 of figure 2).

Accordingly, the change in voltage at the output of the integrator 9 in the interval 33-35 is determined by the expression

35

 and,

ito n, i cd p, g, „. -g; n city, -. -

Rjc

where n, is the number of elementary time intervals terval, 33–36,

In addition, until the end of integration, the device works in a similar way, but with the only difference that the bits begin by closing the key 2 at odd times 35-33.

646

The voltage changes at the integrator in the intervals in the intervals. When the key 2 is open, are determined by the expression

-

 - uto Pgt-g: 2t-

-and, --.- (4)

where m is an integer corresponding to conditionally 2emfe11. The voltage variation at the integrator output in the intervals when the switch 2 is closed is determined by the attenuation

kiT -rr, t: Blcii-iiJlni. p AJE2.H ...., 2n, r R g R.C

b. t

(five)

where m is an integer corresponding to

condition.

At time 53, the third key 7 opens, disconnecting the voltage U) and closing the keys 2,3. The closure of the key 3 is produced by the element And 14 on the incoming signal on it allowing the signal from the output of the trigger 23. The law of change in the conductivity of the second key 3 is shown in graph 26 of Fig.2.

Two currents from source 1 enter the input of integrator 9 in the range 53-56: through switch 2 and resistor 4, as well as through switch 3 and resistor 5. The voltage at the output of integrator 9 linearly decreases until time 56, which is determined similarly to that described above. The change in voltage at the integrator output in the time interval 53-56 will be

whether

53.56

- 1T about 5. 56

V- -f p (6)

After unlocking the key 2 at the moment 56, the voltage at the output of the integrator 9 continues to decrease linearly. The rate of its change is determined by the discharge current from source 1 through resistor 5.

In this case, we assume that

Rj 100 R

(7)

and

in the range of 56-55 will act

and.

discharge current - QQ-g-

When the voltage at the output of the integrator 9 passes through zero at time 55

from the comparator 11 signal, the signal 14 changes to the element 14, which changes its state, as a result of which the key 3. spreads out.

The change in voltage at the output of the integrator 9 in the interval 56-55 is equal to:

  TI iiUleiS ...

R-c

(eight)

A complete change in voltage at the output of integrator 9 for the entire span of 34-35 is zero, therefore, summation (4), (5), (6) and (8) will yield:

1t- ti a. Sj ± 4. TI ta. -

(iiO

y P i blL i D-l. tJ n-J + y n ol lй; lЙ - - x R. R f

(i

mri

  R, C

mt2

0 4to nim-ij jjj ,.

kr.

„IiTUtjj ns3. °

 0

(9)

From the last expression, taking into account. (2) and (7), we get

v11

 5 N, -5 -Cpa.-gt "," 111

where N is the number of elementary time intervals included in the integration interval U, P-.1.

Numbers

and n

 73

the senior and lower bits of the obtained measurement result are determined respectively. To obtain an output code in the form of a decimal number of a-10 with equal or multiplicity of the nominal value of Ux with Uj, it is necessary to choose N and Ug as numbers p ai xY.

G:; . -

in the device, pulses that carry information about the values of the high and low bits are formed at the outputs of elements 13 and 15, to the inputs of which impulses come from the output of generator 18. The passage of these pulses at intervals of 33 ... 56 through element 13 is resolved by trigger 21. this is the filling of the senior decades of the counter 16 in accordance with schedule 28 in FIG. 2. Element And 14

0

five

0

25

thirty

35

40

45

50

55

permits the passage of the same pulses through an AND 15 element in the range of 53-55 to the lower bits of the counter;

8 moment 55, the counter 16 will finish counting the pulses and a code corresponding to the expression (Yu) will be generated in it. The found value of the measured value is transmitted to block 17, indicator 17. In the interval 55-57 up to the beginning from the moment 57 of the next measurement, when all the keys 2,3 and 7 are open, the zero initial conditions of the integrator 9 are set, the zeros entering into device operational amplifiers.

Corrections in the range 55-57 are made by closing the output of comparator 11 with the integrator input.

9 through the key and analog storage device (not shown). The closure of the correction key forms a negative feedback loop, which acts to establish the initial conditions of the integrator, creates on the analog storage device a voltage sufficient to establish the zeros of the integrator's operational amplifiers and the second comparator. When measurements are taken, the correction key is open, and the analog memory device stores the voltage, providing compensation for the offsets of the zeros of the integrator operational amplifiers and the second, comparator.

Accuracy is higher, since errors that occur when switching on the discharge current are excluded, errors of the device are excluded depending on the amplitude of the measured voltage and on the interference of the supply network.

Claims (1)

Invention Formula An analog-to-digital converter containing three keys, the outputs of which through corresponding first, second, and third current-limiting elements made on resistors are connected to the input of the integrator, the input of the first is an input bus, the input of the second key is connected to the output of the reference voltage, the output the integrator is connected to the first input of the first comparator, the second input of which is common, the first element AND, the output of which is connected to the first input of the primary. about GO pulse counter, pulse generator, the output of which is connected to the input of the second pulse counter, the third pulse counter, the second, third, fourth and fifth elements And, the first and second triggers, characterized in that in order to catch accuracy and simplify the converter, , entered the second comparator and the display unit, whose inputs are connected to the corresponding outputs of the first pulse counter whose second input is connected to the output of the third element And, the first input of which is connected to the first output of the first trigger, the second the input is combined with the first input of the first element I, the input of the second pulse counter, the first inputs of the fourth and fifth elements I, the second input of which is combined with the first input of the second trigger and connected to the output of the third pulse counter, you the stroke of the fifth element I is connected to the second input of the second trigger, the output of which is combined with the control input of the first key and the first input of the second element I, the output of which is connected to the control input of the second key and the second input of the first element I, the control input of the third the key is connected to the second output of the first trigger, the input of the third key is connected to the output of the voltage source, the first input of the first trigger is combined with the input of the third pulse counter and connected to the output of the second pulse counter, W The input of the first trigger is connected to the code of the fourth element AND, the second input of which is connected to the output of the second comparator, the first input of which is connected to the output of the integrator, and the second input is the bias voltage bus, the output of the first comparator is connected to the second input of the second element I. five 0 L. IXX I .i JL l Ji-L. . dgat uI fi92 Editor M. Tovtin Compiled by A. Titov Tehred, L. Serdyukova Order 5576/56 Circulation 900 Subscription VNSHSHI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, 1d. Uzhgorod, st. Project, 4 Proofreader V.Girn to