SU1335988A1 - Device for computing elementary functions - Google Patents

Abstract

The purpose of the invention is to expand the class of tasks to be solved by allowing simultaneous calculation of functions; A device for calculating the elementary functions is known, which contains the first, second and third counters, the first and second groups of elements AND, the first and second elements OR, the first and second binary multipliers,: a pulse adder, the first input of which is connected to the output of the first element. OR, the inputs connected to the outputs of elements AND of the first group, the signal inputs of which are connected to the outputs of the corresponding bits of the first counter, the control inputs with the outputs of the corresponding bits of the second counter and signal inputs and elements AND of the second group, the outputs of which are connected to the inputs of the second element S1I, and the control inputs to the outputs of the corresponding bits of the third counter. To achieve this goal, the third and fourth elements of the AND group, the third and fourth OR elements, and the combined addition and subtraction unit are introduced into the device. The output of the latter is connected to the input of the second counter, the outputs of which are connected to the control inputs of the corresponding elements AND of the third group, the outputs connected to the inputs of the third element OR. The output of the third element OR is connected to the second input of the pulse adder via the first binary multiplier, the output of which is connected to the first input of the combined addition and subtraction unit, the second input of which is connected to the output of the second element I. The signal inputs of the elements of the third and fourth groups are connected respectively the outputs of the third meter and with the control inputs of the corresponding elements of the fourth group, the outputs of which are connected to the inputs of the fourth element OR, the output connected through the second two primary multiplier with the input of the first counter. The input of the third counter is the input of the device. 2 Il. (L 00 co. SD Y 00 00

Description

one

The invention relates to automation, computational and measurement techniques, and can be applied in software process control systems, digital linearization devices for primary transducers, electronic modeling devices, specialized computing complexes, etc.

The purpose of the invention is the extension of the class of tasks to be solved by one-time, x-th calculation of functions y x e;

xi 2m

Fig. 1 shows a block diagram of the device; Fig. 2a shows one of the possible variants of the combined addition-subtraction unit; Fig. 26 shows one of the possible variants of a pulse adder.

The device contains an input 1, counters 2-4, a group of elements And 5-8, elements OR 9-12, binary multipliers 13 and 14, a combined block 15 for adding and subtracting pulse sequences, a pulse adder 1 6.

The combined addition-subtracting unit (Fig. 2a) contains: it inputs 17 and 18, output 19, D-flip-flop 20, element OR 21, delay element 22 and And 23 element, signals 24 at the C-input of D-flip-flop 20, signal 25 at the output of the D-flip-flop 20, the signal 26 at the output of the element OR 21.

The addition unit (Fig. 2b) contains a delay element 27, an AND element 28, inputs 29 and 30 and an output 31.

Counter 2, group 5 and the element OR 9 form the third binary multiplier, controlled by counter 2. Counter 3, group 6 and the element OR 10 form the fourth binary frequency multiplier, controlled by counter 2. Counter 4, group 7 and the element OR 11 form the fifth binary multiplier controlled by the counter 3. Counter 2, group 8 and the element OR 12 form the sixth binary multiplier controlled by the counter 3. The bit output of the counters-dividers of the binary multipliers is connected to the signal inputs of the elements AND the corresponding groups with the control inputs AND elements are connected The discharge outlets controlled Counters Yu- jKKX, wherein if the input ele35988

And the group of co (ch iyen with the junior digit of the counter-divider, the second input is connected with the senior digit of the control counter, and vice versa.

The outputs of the elements And the corresponding groups are connected to the inputs of the corresponding elements OR. Input 1 of the device is input to counter 2,

d output of the element OR 9 is connected via a binary multiplier 13 to the input of the counter 4, the output of the element OR 11 is connected to the input 29 of the pulse adder 16, the input 30 of which through

IT, the binary multiplier 14 is connected to the output of the element OR 12, and the output 31 of the pulse cummator 16 is connected to the input 17 of the combined addition-subtracting unit 15, the input 18 of which

.; (, is connected to the output of the element OR 10, and the output 19 is connected to the input of the counter 3.

In the initial state in the counter 3 the initial number is written, and the counters

5 2 and A are in the zero state.

The operation of the combined addition-reading unit 15 is illustrated by the timing diagrams shown in Fig. 2a.

thirty ,, " "

The device works as follows.

Input 1 receives a pulse sequence X. The increments dx of this sequence arrive at 5 the input of counter 2 and cause the output of the third binary multiplier to increase the dv described by the equation

where m is the conversion factor of the counters,

45

At the input, p of that binary multiplier (at the input of counter 4) are increments

dp k, d) f, (2)

where k, is the transfer coefficient of the binary multiplier 13.

 These increments cause the appearance of the increments dp at the output of the fifth binary multiplier, which are fed to the input 29 of the pulse adder and are described by the equation

55

(3)

d, i-dP

where y is the current value of the number in

counter 3.

Solving together (1) - (3), we get dft k k, dx. (4)

f m

t

The increments dx of the pulse sequence X entering the input of counter 2 also cause the appearance at the output of the sixth binary multiplier of the increment d5, described by the equation

d. (5)

tn

The input 30 of the pulse adder increments

dz k-. m

The operation of the pulse adder is described by the equation

dl d + dz. (7)

The increments dy of the pulse sequence y, coming from the output 19 of the combined addition and subtraction unit to the input of the counter 3, cause the output of the fourth binary multiplier to be incremented by d, described by the equation

d - dy.

 ha. The operation of the combined addition-reading unit 15 is described by the equation

dy dl + dy - d. (9) Having decided to jointly (4), (6), (7) - (9), we get

(1.0)

Claims (1)

The invention The device for calculating elementary functions, containing counters from the first to the third, a group of elements AND from the first to the third, elements OR, from the first to the third multiplier, a pulse adder, the input of the device is connected to the information d the input of the first counter, the outputs of the higher bits of which are connected to the pulse inputs of elements AND of the first group, the outputs of which are connected to the inputs of the first element OR, vyho15 Dy of the second counter are connected to pulse inputs of elements AND of the second group, the outputs of which are connected to the input of the second element OR, the outputs of the third counter are connected to the potential2Q element inputs of the elements of the second group, characterized in that, in order to expand the class of tasks to be solved due to the simultaneous k, x -:, J i i 5 25 calculus function, It contains the third and fourth groups of AND elements, the third and fourth OR elements, the read-out (8) read block, the multiplier, the output of which is 30 connected to the input of the first operand of the adder, the output of which is connected to the input of the first operand of the adder-subtractor, whose output connected to the information input of the third (6) 16 x 2Sh dy k,,,. dx i i. (jx + k. -. m X Integra (in): a Do (get  (eleven) J y m JMX 11oo k, x 25 counter, the outputs of which are connected to pulse inputs and elements And the fourth group, the outputs of the elements And the third group connected to the inputs of the third element OR, the output of which 40 is connected to the input of the second operand of the adder-subtractor, the outputs of the elements of the fourth group are connected to the inputs of the fourth element OR, the output of which is connected to the information input of the first multiplier, the outputs of the lower bits of the first counter are connected to the potential inputs of the elements of the first, third and fourth groups , the output of the second element OR is connected to the information input of the second multiplier, the output of which is connected to the information input of the first counter, the output of the second element OR is connected to the input of the second op eran (one) (T2) will get (13) the proposed class resolved for x 2Sh the counter, the outputs of which are connected to the pulse inputs and elements of the fourth group, the outputs of the elements of the third group are connected to the inputs of the third element OR, the output of which connected to the input of the second operand of the adder-subtractor, the outputs of the elements of the fourth group are connected to the inputs of the fourth element OR, the output of which is connected to the information input of the first multiplier, the outputs of the lower bits of the first counter are connected to the potential inputs of the elements of the first, third and fourth groups, the output the second element OR is connected to the information input of the second multiplier, the output of which is connected to the information input of the first counter; the output of the second element OR is connected to the input of the second opera n 55 yes adder. 17 17 g 25 21 GB gz L irij 2 Editor N.Egorova Compiled by Z. Shershiyeva Tehred M. Holanich Order 4048/43 Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, l. Project, 4 Proofreader S. Shekmar