SU1324106A1 - G-flip=flop - Google Patents

Abstract

The invention relates to computing, can be used to indicate the end points of parallel transients. The purpose of the invention is to reduce the load on the inputs of the G-flip-flop. The device contains the RS-trigger, the elements AND-NOT 4, 5, the element OR 6, the element AND 7. To achieve this goal, new connections have been introduced into the device. 1 il. I (с s: RR to cd

Description

one

The invention approaches computational techniques and can be used to indicate the end points of parallel transients.

The aim of the invention is to reduce the load on the inputs of the G-flip-flop.

The drawing shows the scheme of the G-trigger.

G-flip-flop contains RS-flip-flop 1 on the first 2 and second 3 AND-NOT elements, the third 4 and fourth 5 AND-NOT elements, the OR element 6 and the AND 7 element.

The output of the element 6 is connected to the first input of the element, 7 and the input of the element 2, the output of which is connected to the first input of the element 4, the second input of which is connected to the output of the element 7 and the first input of the element. 6, and the output - with the input element 3 and the second input

1324106-2

In the case of a reverse switching of signals at inputs 9 and 10, element 7 first switches and at its output a zero logic signal appears, and

5 thereafter, the same signal appears at the output of element 6, the latter triggers the switching of the RS flip-flop 1, and first a single logical signal 0 appears at the output of element 2, and then zero at the output of element 3. The appearance of a single logical signal at the output of element 2 does not cause switching of element 4, since at the input of the latter it has a 5s zero logic signal from the output of element 7. Switching RS-flip-flop 1, in turn, causes switching of element 5, and output 8 there is a single logical

element 5, the first input of which is 20 signal, which completes the transition

dinene with the output of element 3, and the output with the output of 8 G-trigger, inputs 9 and 10

which are connected respectively with

the first input of element 6 and the second

input element 7.

G-trigger works as follows.

If in the initial state at inputs 9 and 10 there is a zero logic signal, then at the outputs of elements 6 and 7 a zero logic signal is also set, at the outputs of elements 2 and. 4 - single, at the output of element 3 - zero, i.e. The RS flip-flop 1 is in the zero state, and a single logic signal is set at the output of element 5 (output 8).

thirty

the process in this phase of the G-trigra operation, which then turns out to be the initial state.

When appearing at inputs 9 and 10 2-5 of single logical signals, the switch switches the element OR 6, and for the appearance of zero signals, the element 7 switches first. These elements can be amplified.

In the proposed G-flip-flop, each input is connected only to the input of one element, which reduces the load on the inputs of the G-flip-flop.

Claims (1)

35 formula invented G-trigger containing RS-trigger on the first and second elements AND-NOT the third and fourth elements AND-NOT, When switching signals at inputs 9 and 10, element 6 first switches and at its output appears a single logical signal, then the same signal appears at the output of element 7. The last invocation of a zero logic signal at the output of element 4 is that in turn, causes the switching of the RS-trigger 1, first a single logical signal appears at the output of element 3, and then zero at the output of element 2, as a result, a single logical signal appears again at the output of element 4, after which Element 5 and a zero logic signal appears at output 8, this completes the transition process in this phase of the G-flip-flop; thirty the process in this phase of the G-flip-flop, which in this case is in its original state. When appearing at inputs 9 and 10 2-5 of single logical signals, the element OR 6 switches first, and when zero appears, the element 7 switches first. These elements must be reinforcing. In the proposed G-flip-flop, each input is connected only to the input of one element, which reduces the load on the inputs of the G-flip-flop. 35 claims G-trigger containing the RS-trigger on the first and second elements of NAND, the third and fourth elements of NAND, 40 AND element and OR element, the output of which is connected to the input of the first NAND element, the output of which is connected to the first input of the third NAND element, whose output is connected to the input of the second NAND element, the output of which is connected to the first the input of the fourth NAND element, the second input of which is connected by the output of the third NAND element, and the output is connected to the output 50 G-flip-flop, the first input of which is connected to the first input of the OR element, characterized in that, in order to reduce the load on the inputs of the G-flip-flop, the first input of the AND element is connected to the output of the OR element, the second input - to the second input of the G-trigger and the output is with the second inputs of the OR element and the third NAND element.