SU1324108A1 - G-flip-flop - Google Patents

Abstract

The invention relates to computing, can be used to indicate the end points of parallel transients. The purpose of the invention. The reduction of the load on the inputs of the G-flip-flop. The device contains an RS-flip-flop, AND-NO elements 4, 5, 2 and the elements OR and I. To achieve this goal, new connections are introduced into the device. 1 il. (L 00

Description

The invention relates to computing and can be used to indicate the end points of parallel transients.

The aim of the invention is to reduce the load on the inputs of the G-flip-flop.

The drawing shows the scheme of the G-trigger.

When switching signals at inputs 9k and lO.k, element 6 first switches. (K + 4) and a single logic signal appears at its output and only after that the same signal appears at element 7 output. (K + Switching elements 7.8 -7.5 causes a sequential switching of elements 7.4-7.2, and then an element

G-flip-flop with four even and no 4, the output of which appears

even-numbered inputs contains an RS-flip-flop 1 on the first 2 and second 3 AND-NOT elements, the third 4 and fourth 5 AND-NOT elements, OR 6.1-6.8 elements and AND 7.1-7.8 elements.

The output of element 6.1 is connected to the input of element 2 and the first input of element 7.1, the second input of which is connected to the output of element 5 and the first input of element 6.4 and the output to the output of an 8 G-flip-flop.

The output of the element 61, where i 2-4, is connected to the first input of the element 6 (i-1). The output of element 7.2 is connected to the first input of element 4, the output of which is connected to the input of element 3 and the first input of element 5, the second input of which is connected to the output of element 3. The output of element 7.J, where 4, is connected to the first input of element 7. ( j-1).

Inputs 9k and 10k, where k 14

connected respectively with the first inputs of elements 6 (k + 4) and 7. (k + 4).

The second input element 6.1 is connected to the output element 6.5 and the second input element 7.5, the output of which is connected to the second inputs of elements 4 and 6.5. The second input of element 61 is connected to the output of element 6. (i + 4) and the second input of element 7. (i-i-4), whose output is connected to the second inputs of elements 6. (i + 4) and 7.1.

G-trigger works as follows.

If in the initial state at the inputs 9.k and lO.k there is a zero logic signal, then at the outputs 6.5-6.8 and 7.2-7. A zero logic signal is also set, at the outputs of elements 2 and 4 - one, at the output of element 3 - zero, i.e. The RS flip-flop 1 is in the zero state, at the output of element 5 is a single signal and the same signal is set at the outputs of elements 6.4-6. and 7.1 and output 8 G-flip-flop,

When switching signals at inputs 9k and lO.k, element 6 first switches. (K + 4) and a single logical signal appears at its output, and only after that the same signal appears at the output of element 7. (k + 4 ) 4 Switching elements 7.8-7.5 causes sequential switching of elements 7.4-7.2, and then element 4, at the output of which

five

0

five

0

five

0

five

0

five

zero logic signal. The latter will cause the switching of the RS flip-flop 1, and first a logical signal appears at the output of element 3, and then zero at the output of element 2. As a result, the sequential switching of elements 7.4-2.7 and element 4, which causes the appearance of a single logical signal at the output of the latter, begins again, after which element 5 switches and at its output a logic zero signal appears, and then the same signal appears at - output element 7.1 (output 8), which completes the transition process in this phase of the G-flip-flop.

When switching signals back at the inputs 9.k and 10.k of the G-flip-flop, element 7 first switches. (K + 4) and a zero logical signal appears at its output, and only after that the same signal appears at the element output 6. (k + 4).

Switching elements 6.8-6.5 causes sequential switching of elements 6.4-6.1, and zero logic signals appear at their outputs, after which RS-flip-flop 1 switches, and first a single logic signal appears at the output of element 2, and then element 3 - zero. Switching RS-flip-flop 1 causes switching of element 5, at the output of which a single logic signal appears. As a result, the sequential switching of elements 6.4-6.1 begins again, at the output of which single signals appear, and then the same signal appears at the output of element 7.1 (output 8), which completes the transition process in this phase of the G-flip-flop, the latter again being in the initial state.

When appearances at inputs 9.k and 10.k are G-three single logic

the signals are switched by the element OR 6 first. (k - "- 4), and when zero appears, the element 7 is switched by the first 7 (k + 4). These elements must be reinforcing.

The proposed G-trigger contains 2N-I-4 two-input elements, where N is the number of inputs of the G-trigger. In this case, in the G-flip-flop, each input is connected to the input of only one AND or OR element.

Thus, the application of the invention provides a small load on the inputs of the G-flip-flop.

Claims (1)

Invention Formula T-flip-flop with n even and odd inputs, containing RS-flip-flop on the first and second elements AND-NOT, third and fourth elements AND-NOT, 2n elements OR and And, the output of the first element OR is connected to the input of the first element AND-NOT and the first input of the first element is AND, the second input of which is connected to the output of the fourth AND-NOT element and the first input of the n-th element OR, and the output to the code of the G-trigger, the output of the i-element OR, where Editor L. Veselovska Order 2972/56 Compiled by O. Skvortsov Techred. L. Oliynyk Proofreader G. Reshetnik Circulation 901 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project 4 Sh f5 20 25 1084 i 2, ..., p is connected to the first input (il) -ro of the OR element, the output of the second AND element is connected to the first input of the third AND – NE element, the output of which is connected to the input of the second AND – NE element and the first input of the fourth AND element -NON, the second input of which is connected to the output of the second element NAND, and the output of the j-ro element I, where j 3, ..., p, is connected to the first input (jl) -ro of the element I, the k-th even input The G-flip-flop, where, ..., p, is connected to the second input (n + k) of the OR element, characterized in that, in order to reduce the load on the inputs of the G-flip-flop, its k-th odd input is connected to P With the first input (n + k) -ro of the AND element, the second input of the first element OR is connected to the output of the (n + 1) -th element AND, the output of which is connected to the second inputs of the third element AND-NES and (n + 1) -th element OR, the second input of the i-ro element OR is connected to the output of the (n + i) -ro element OR, and the second input of the (n + 1) -th element AND, the output of which is connected to the second inputs of the i-ro element And (n + i -ro element OR.