SU1324029A1 - Device for built-in test equipment - Google Patents

Abstract

The invention relates to a technique: built-in automated control and can be used to control various digital blocks. The purpose of the invention is the extension of functional capabilities due to the possibility of operation in analyzer modes and in generator modes of synchronizable sequential states, as well as ensuring the possibility of working with changes in the size and duration of a pseudo-random sequence of states. The device contains a control signal encoder, three adders, two multiplexers, three switches, an encoder. The device can perform the functions of generator I (pseudo-random code generator, generator of incremental sequence states, generator of decrementable sequence states), a counter (number of transitions, number of transitions with comparison of the obtained value with a reference one), adder with control , signature analyzer. 1 piece, 4 tab. c (L OQ o 4 O to co

Description

The invention relates to a built-in aptematized control technique and can be used to control various digital blocks as test generators and analyzers.

The purpose of the invention is to expand the field of application of the device by providing the ability to work in the analyzer modes of the incremental generator of successive states, as well as to enable it to work with a change in the size and duration of a pseudo-random sequence of states.

The drawing shows a diagram of the device.

The device contains a delay element 1, made on the counter, a control signal encoder 2, a group of outputs 3, a control signal encoder, a group of control inputs A of multiplexer 5, output 6 of which is connected to the input of adder 7, sum

Depending on the inclusion of the device for the built-in test control, it can perform the functions of either a response analyzer of the tested functional unit on the specified test actions. The device is eight-charge and allows extensions 8 and 9 to module two, the group of pr -25 test generator, or wired discharge outputs 10 of register 11, AND-NO 12, trigger 43, encoder 14, switches 15 and 16, group of elements is NOT 47 , unit 18 comparisons, switch 19, multiplexer 20, access to the required number of IS-NE 21-23 components, triggers 24-26 ,, series.

pulse shaper 27, the element Device operation mode is NOT 28, information input 29 is after- in accordance with the table. 1 on the command word submission, the information group of inputs X8-X12, the incoming groups of inputs 30 and 31 communi- cation encoders 2 and 14. the instructor, the group of information inputs

32 switches, output 33 of the encoder, control signals, a group of inverse bit outputs of register 11, an output of 35 lower inverse bits of a register connected to the input of the adder 8, a group of information inputs 36-38 of the switch, a group of outputs 39 of the switch, a group of information inputs 40 of the adder groups of inputs 41 and 42 of the comparison unit, information input 43 of the multiplexer, input 44 of the control signal encoder, outputs 45 and 46 of the control signal encoder, invert 47 reset of the adder, group of output 48 of the control encoder, The outputs 49 and 50 of the control signal encoder, the information inputs 51-53 of the switch, the output 54 of the transfer of the adder, 55 1 which prohibits the passage of the control input 55 of the multiplexer, the pulses TI through the IS-NE 23 element and the output 56 of the control encoder 55 inverted inputs 57 and 58 of the control signal encoder, inputs 59

forms a positive edge of the pulse on the input of the NU device. This impulse goes to the element AND-NOT 22,

go type

and 60 control signal encoders, inverse outputs 61 and 62 of the multiplexer - outputs of the indication of the result and output of the indication of a device error, respectively, outputs 63 of the parallel word supply, group of inputs 64 of the setting of the operating mode, outputs 65 of the start of operation of the device (CU), start 66 , synchronization input 67, the first: (CT) and second (I) inputs 68 and 69 set the operation mode, respectively, and device feature output (PS) 70. The device for embedded test control is implemented in the form of an LSI and is intended for use as part of computing equipment and digital automation devices as a core for constructing embedded self-diagnostics circuits of various ROMs, as well as of production types.

free logic.

Depending on the inclusion of the device, the built-in test control can perform the functions of either a generator of test actions or the provision of up to the required number of bits.

analyzer of the reaction of the tested functional unit on the specified test actions. The device is eight-charge and allows the test effects to be extended, or to reach the required number of bits.

The device works as follows.

Inclusion and preparation for work

devices start for all modes of operation in the same way - by triggering a start signal.

Asynchronously, the Start signal comes on inverting D and

R inputs of the trigger 13, removes its retention at zero, and the trigger 13 through the next pulse TI is set to 1, which allows the passage of pulses TI through the elements AND NOT 12

and 23, forms a negative edge of the pulse at the output of the NU device, and also removes the retention of 1 delay from the Li. Through In cycles of line 1 Z. forms the output potential

1 which prohibits the passage of TI pulses through the element AND-NOT 23 and

forms a positive edge of the pulse on the input of the NU device. This impulse goes to the element AND-NOT 22,

It generates a potential 1 at input 60 (X6) of encoder 2, which sets all device nodes to their initial state with control signals formed in encoder 2, in accordance with the equations of operation of the outputs.

33 X6-X7jX8VX6X7 X9UH6X7 X10

X11; X12UH6 X7 X1GO-X1 1-X12

48 younger H1X6-X8.X9VX5-Hb- B

Xg-xio

48 which became X8-X9VX5 -Hb.H8-XE

ХХ10.Х11

46 X1 X8VX1 X9VX5-X8 X9X10VX5 X8 -X9 "X11VX5 X8 X9 XI2VX6-- X8VX6 KX9VX6 X10VX6 X11VX6 X12

That v 20

25

3 Junior HBHb-X8 .X9VXbX8j X9VX6 X8 X9VX5- X8 JC9 -Xl 1VX5- X8 X9 "X10.X12VX5-.X8-X9-X16VX6-X9J Xl 1VX6 X9-XIO-X12VX6-X9-X9JX-1 XX

 X9-X10-X11

W senior X8-X9-X10 X1J VX X9j

XXJO-X12VX1OC8-X9VX6-.X8 - X9VX5-X8

X9 X9jX10

45 - X8 X9-X10-X11VX8.-X9-X1Qx

VX11VX8-X9-X10-X12

55.-X8 XTO X11-X12VX6 X8 XX9-X10X11: XI2VX6X8X9 Xl1 X12 x

XX10;

56 X6-X8-X9-X10-X11-X12-X7

49 X1 2-X5-X6-X8, -X9 - X10-X11 "X1 - X5 X6; X8-X9-X10 XI 1VX1.-X2.-X5 X6 ..- X1J.-)

50 XI: X5-X6-X8-X9-X1.0-X11VX1 X5-Hb-X8uX9-X10-X11UH1 X5 Hb X8 X9-X11-X12

de. - conjunction,

V - disjunctions ..

After the termination of the impulse NU, the next impulse TI sets the trigger 24 to 1 and at the input 60 of the encoder the potential O is set, coordinated in accordance with the equations

thirty

eg

.ten

and the specified command translates the device- commutes code 01, as well as on up50

If the device operates in one of the modes of the test effects generator, the outputs of the switch 19 are transferred from the disconnected state to the active code of the encoder 2 in accordance with the equation of its operation.

Setting the Start signal to 1 causes the ra-. device bots and switching output 55 of switch 19 to a disabled state.

Multiplexer 5 with a combination of 00- on control inputs 4 switches

equal inputs of the multiplexer 4, code 01 is formed, i.e. input 6 of the adder 7 receives the output of the adder 9 modulo 2, which contains 3, 4, 5, 7 bits of the register 11, and the code 01, i.e., is generated simultaneously on the control input group of the switch 15. the groups 39 and 40 of the inputs of the adder 7 receive the contents of register 11, as a result of which on register 11 each pulse TI is shifted by one bit to the left, and at the lower bit a convolution mod 2 of the 3rd, 4th is entered, 5th

 g

13240294

to the input 6 of the adder 7 output

NOT 28, with a combination of 01, is inverse

summer code 9 modulo2, with

g

O

combinations lOj - adder output

five

0

five

8 modulo 2, with a combination of 112 - the potential of O.

The multiplexer 20 at O on the control input 55 switches the output 54 of transfer of the adder 7 to the output 62 of the device’s sum and the output of the equality block 18 of the comparison to the output 61 of the device’s equality 61, and at 1 to the input 55 switches the output of the trigger 25 for a fault to the output 62 of the device’s sum and the output of the trigger 26 health to the output 61 of the device.

The switch with the combination 00 on the control input group commutes to the input group 39 of the adder 7 the inverse information from the input group 38, with the combination 01 the inverse output group 34 of the register 11 with the South combination the third input group 37, with the combination 11 - the first group inputs 32.

The switch 16 at O on the control input switches the input 42 from the comparison unit 18 to the inverse information from the outputs of the encoder 14, and when 1 0 on the control input it indicates the inverse value of the data input-outputs of the device. wah

I. Pseudo-random code generator mode. At the inputs BX, B is served. eg Oh, the value of the signals at the inputs of PS and CT indifferently.

During the NU pulse, the input 6 of the adder 7 is fed 1 and the input 47 of the adder 7 also passes 1, which zeroes both terms of the adder 7, thereby registering the register 11 with a code. In tact,. following the termination of the NU signal, the switch 19 on the device input codes

.ten

equal inputs of the multiplexer 4, code 01 is formed, i.e. input 6 of the adder 7 receives the output of the adder 9 modulo 2, which contains 3, 4, 5, 7 bits of the register 11, and the code 01, i.e., is generated simultaneously on the control input group of the switch 15. the groups 39 and 40 of the inputs of the adder 7 receive the contents of register 11, as a result of which on register 11 each pulse TI is shifted by one bit to the left, and at the lower bit a convolution mod 2 of the 3rd, 4th is entered, 5th

7th bits Thus, an 8-bit pseudo-random sequence generator is implemented.

The length of the pseudo-random sequence is specified by binary codes at the inputs X10, XI1, XI2 in accordance with Table. 2

In block 18, comparison is constant.

compare the current value of the register- (On the n mode is similar to the previous

11 and the final state of the device specified by the inputs of the device X10, Xll, XI2. When these states coincide, the signal 1 arrives at the input 44 of the comparator 2 and the register 11 is set by the next TI to the state 01., i.e. returns to the exception of the state of the outputs of the second control unit 14 (Table 4) and the potential set at the input B, which must be equal to iV

In this mode, the subtraction is carried out by applying to the input 39 of the adder 7 the GG code,.

This mode is intended for the prog returns the initial state. .

If it is necessary to form the number of states of the Pseudo-20 Generator to verify the correctness of storing an infor- mal random sequence, there is more madium in the permanent storage device than one device allows.

In, you can use several. When sharing such non-synchronous working devices, how many devices working in this case all devices must have 25 of this mode. X12 1 for the elder are different from each other values of the input device a, for the remaining XI2 O, clauses X10 ,, XII, X12. which ensures the transfer of the sum and the output of equality from the younger devices.

After preparing for operation, the random random codes of the eight devices 30, the instrument performs the summation as the product S; (see the information input / output stupid in each clock cycle, the sum is accumulated in register 11. The initial state of register 11 is OOiE.

The maximum number of states of such a composite pseudo-oscillator. 2).

P S; .

I rb

For example, for two devices, in one of which the number of states is S, and in the other Si, the total number of states is 64,770.

However, in the generator mode of incremental sequential states, the generic state is from 00 to the output of the encoder 14, defined by the code at the inputs X10, XI1, XI2, in accordance with Table. 3,

The state of the inputs B and B is equal to

nil

40

 ABOUT

First impulse ti after signal

35

Upon admission to the input CT. signal, indicating that the device for the built-in test control is forming, working in the generator mode, the address of the last cell of the drive of the checked ROM, which stores the checksum for this ROM drive, the encryption control signal according to the equations, under which the device makes a comparison on the information comparison unit 18, read from the ROM

WELL register 11 is set to co-Q with a checksum obtained from

This is 00, each next TI pulse on register 11 records its old state plus one f. up to a value that matches the outputs of the encoder. The next TI pulse is to register code 11 in register 11. The number of generator states of the incremental successive states can be increased up to 55

register 11. In the case of coincidence on the high-level device at output b1 Out 11, an inverse value of the health trigger 26 appears, equal to O and indicating the truth of the information stored in the ROM. In the event of a mismatch, the information O is formed at the output. 62 Out older device.

The addition of the corresponding number of described devices in a similar mode. The CT and PS inputs used in this mode can have any value.

Iii. In this mode, the generator of decrementing sequential states provides for switching on and operation of the device in this mode except for the output of the second control unit 14 (Table 4) and the potential set at input B, which must be equal to iV

In this mode, the subtraction is carried out by applying to the input 39 of the adder 7 the GG code,.

This mode is intended to check the correct storage of information in a permanent storage device.

After preparing for operation, the device performs summation of the information appearing in each cycle to the information inputs / outputs of information, accumulates the sum in register 11. The initial state of register 11 is OOiE.

40

35

Upon admission to the input CT. signal, indicating that the device for the built-in test control is forming, working in the generator mode, the address of the last cell of the drive of the checked ROM, which stores the checksum for this ROM drive, the encryption control signal according to the equations, under which the device makes a comparison on the information comparison unit 18, read from the ROM

five

register 11. In the case of a match on the high-end device at the output of the B1-OUT-11, an inverse value of the health trigger 26 appears, equal to, O and indicating the truth of the information stored in the ROM. If there is a mismatch, the information O is generated at the output. 62 Out older device.

15

For the organization of the check sum, it is necessary to sum up and carry over from the higher bit. But in the older device, the output of output 62 is 2. used to signal that the checksum does not match. Therefore, at the output 56 of the encoder 2 in this mode, 1 is formed in accordance with the equations, which includes the driver 27, the output of which forms the inverse value of the transfer output 54 of the adder 7, as a result, when connecting the input-output of the MS from the older device to the input the sum of Bx 21 junior device is implemented checksum taking into account the transfer from the senior bit.

Iv. The signature analyzer mode compares the reference signatures. In this mode, a signal is sent to the input of the BxX device, the signature of which must be obtained. The reference signature is read from the DO-D7 I / O.

In the signature analyzer mode, the switch 15, sumator 7, register 11, works in the same way as in the signature generator mode, the difference is that the initial state of the register is 11-00 and the multiplexer 5 doesn’t switch after the NU pulse, but switches permanently input 6 adder 7 output adder 9 modulo 2.

In this mode, the switch 15 commutes to a group of 39 inputs of the sum of the .7 cdd OCh. The first multiplexer 5 switches the output of the second adder 8 modulo 2 to the first input 6 of the adder 7. At the input 35 of the adder 8 modulo 2 arrives the inverse low-order value of the accumulating adder 11.

Thus, if the low-order bits of register 11 coincide with the value of the signal at the input

At the output of the first adder -8 modulo 2, the potential O, i.e. register 11 is written to the value (old). When changing the information at the input of the BxZ device at the output of the adder 8 modulo 2 potential 1 is formed, then the adder 7 adds a unit to the contents of register 11 and the result is written to register 11.

When O is received at the CT input of the device, the obtained value of the number of transitions of the analyzed signal is compared with the reference one, similarly to the previous mode.

Upon receipt (simultaneous) about the inputs of the CT and PS device signals at the outputs. 62 and 61 older devices are configured in the same way as in the previous mode.

Vi. Signature Analyzer Mode

In this mode, the device receives, at the CT input, a 35-pin signal 11U signal arriving at

20

25

thirty

29 information input device. The duration of the signature generation gate is determined by the duration of the START signal minus

The properties of this register 11 are compared with the input-output DO-D7 of the device in the same way as in the previous mode.

When the information coincides on the comparison unit 18, an O is generated at the output B1 of the VChX of the device, signaling the coincidence of the information. If the signatures do not match, at block 18 of the comparison, O is generated at the output 62 of the Device Outlet 62, informing about the incompatibility of the signatures. When signals are simultaneously applied to the inputs W and the PS of the device in the case of a comparison of signatures, O is formed at the output 61 of the device's Outlet, informing about the correct signature at the last control point if several test points were analyzed sequentially.

V, the mode of the transition number counter DON with the comparison of the obtained value with the reference one.

In this mode, the switch 15 commutes to a group of 39 inputs of the sum of the .7 cdd OCh. The first multiplexer 5 switches the output of the second adder 8 modulo 2 to the first input 6 of the adder 7. At the input 35 of the adder 8 modulo 2 arrives the inverse low-order value of the accumulating adder 11.

Thus, if the low bits of register 11 coincide with the value of the input signal set15

ten

20

25

thirty

In this mode, the device receives, the signature 11U of the signal arriving at

29 information input device. The length of the signature generation gate is determined by the duration of the START signal minus

first pulse pulses Th.

The switch 19 is constantly open, so in this mode, reference signatures can be obtained. The initial state of the register is 1 1 - 00. Unused inputs CT, BX, PS should be equal to 1.

The multiplexer 5 commutes to the input 6 of the adder 7 the inverse output of the adder 9 modulo 2. The information groups of the inputs 39 and 40 of the adder 7 receive the values of register 11 for each TI pulse, and the old contents, which are shifted to the left, are written to register 11

and junior bit is recorded re; the result of the summation of vix mod 2 of the 3rd, 4th, 6th, 5th, .7th bits of the register 11 and. input value of the input B of the device.,

Thus, the mode of operation of signatures of the analyzer in the device is realized.

VII. Conversion count mode.

This mode is designed to obtain reference values of the number of transitions of the analyzed signal. The adder 8 modulo 2, the multiplexer 5, the switch 15, the adder 7 and the register 11 operate in the same way as in the count mode of the transitions with the comparison of the obtained value with the reference one. In this mode, the switch 19 is open, and the switch 16, the multiplexer 20 and the comparison block 18 do not work.

Thus, the invention is secured. -i HBaeT operation of the device in the modes of the pseudo-random code generator, the generator of incremented sequence states, the generator of decrementable sequence states, the number of transitions counter, the number of transitions with the comparison of the obtained value with the reference, the adder with the comparison of the obtained sum with the control, signature analyzer with comparison of received and control signatures and signature analyzer.

Claims (1)

Invention Formula Device for embedded test control containing a control signal encoder, the first trigger delay element executed on the counter, the first IS-NOT element, two switches, the first multiplexer, i-register, adder, two modulo-two adders, and the device start input is connected with the reset input and inverse of the first trigger, the output of which is connected to the inverted reset input of the counter, with the third input of the first AND-NOT element, the output of which is connected to the synchronous input of the register, the information inputs of which are connected to the outputs the first adder, the first group of informational inputs of which is connected to the index group of outputs of the first switch; the enabling input of the first adder is connected to the output of the first multiplexer, the first and second iy (1urmament inputs of which are connected to the first and second adders modulo two. accordingly, the first group of outputs and the first output of the control signal encoder are connected to the group of control inputs and control path of the first and second switches, respectively, one device is connected to the input of the first trigger, a group of direct bit outputs of the register is connected to a group of inputs of the first modulo-two adder, the third information input of the first multiplexer is connected to the zero potential bus of the device, the first input of the operation mode of the encoder control signals, characterized in that, in order to broaden the field of application by providing the possibility of working in analyzer modes and in generator modes of incremental sequences of the gratuitous states, as well as the ability to work with a variation in the size and duration of the pseudo-random sequence of states, it contains the second, third and fourth triggers, the encoder, the group of elements NOT, the third switch, the comparison unit, the element NOT, the driver: the second, third and fourth elements of the NAND and the second multiplexer, the device's synchronous input connected to the inverse of the first element of the NAND, to the first inverse of the second element of the NAND, the output of the first AND of the NAND connected to the input the second, third and fourth flip-flops, the output of the first flip-flop is connected to the direct inputs of the second and third AND-NOT elements and the first direct input of the control signal encoder, the group of inputs of which is connected to the group of inputs for setting the device operation mode and the group of inverse information inputs of the second switch, the group of direct information inputs of which is connected to the group of outputs of the elements of the HE group and with the first group of information inputs of the first switch, the second and third groups of the infor which inputs are connected to buses of zero and unit potentials of the device, respectively, a group of inverse bit outputs of the register is connected to a fourth group of information inputs of the first switch and through a group of information inputs of the third switch with inverse 11 HbtNfo device outputs, the group of inputs of the elements is NOT a group of information inputs of the parallel word feed of the device, the output of the second AND-NOT element is connected to the counting input of the delay counter, the overflow code of which is connected to the inverse input of the third IS-NOT element and the second inverse input of 132 The iporo of the NAND element, the output of the third element of the NAND is NOT connected to the D input of the second trigger, the first input of the 4th element is NAND and is the output of the device start feature, the output of the 4th NAND element is connected to the second forward input of the encoder control signals, the second inverse input of which is connected to the inverse output of the pulse former and is the transfer output of the device, the information input of the pulse former is connected to the transfer output of the first adder and the first information input ggerov respectively, the seventh output encoder control signals coupled to the inverted reset input of the first adder, a third straight entrance encoder control kntsih signa J5 catch coupled to an output Equals comparing unit and vtorgm data input of the second multiplexer, the third and fourth information inputs of which are connected to the outputs 20 of the third and fourth flip-flops, respectively, the first group of inputs of the comparison unit is connected to the inverse inputs of the second switch, the second group of comparison inputs of the second multiplexer, the first and second 25 dinenees with the direct discharge group, the inverse outputs of which are output characteristics of the result and device errors, respectively, the inverse of the resolution input of the comparator unit is connected to the second input of the setting of the device operation mode, the output of the second trigger is connected to the second input of the fourth NAND element, the second second encoder output control signals coupled to control input 35 of the third switch, the second set of encoder outputs actuating signals soe- register moves and with the second group of information inputs of the first adder, the output of the element is NOT connected to the input of the first modulo two adder, the first input of the second adder and the fourth information input of the first multiplexer, the input element is NOT a serial input of the information word, and the inverse output the first bit of the register is connected to the second input |, the house of the second modulo-two adder, T Oh oh ABOUT ABOUT 01 10/1 about 0/1 2402912 A group of control inputs of the first multiplexer, the third and fourth outputs of the control signal encoder are connected to the synchronizer of the pulse generator and the control input of the second multiplexer, the fifth and sixth outputs of the control encoder of the control signals are connected to the D inputs of the third and the fourth of the flip-flops respectively, the seventh output of the control signal encoder is connected to the inverse reset input of the first adder, the third direct input of the control encoder the control signal J5 lov connected to the output Equals comparison unit and with the second information input of the second multiplexer, the third and fourth information inputs of which are connected to the outputs 20 of the third and fourth flip-flops, respectively, the first group of inputs of the comparison unit is connected to the inverse inputs of the second switch, the second group of inputs of the comparison is connected to the group of direct discharge of the high register moves and with the second group of information inputs of the first adder, the output of the element is NOT connected to the input of the first modulo two adder, the first input of the second adder and the fourth information input of the first multiplexer, the input element is NOT a serial input of the information word, and the inverse output the first bit of the register is connected to the second input |, the house of the second modulo-two adder, T Generator incremental successive states Generator of decrementing successive states Conversion Count Conversion count counter comparing the value obtained with the reference Adder with a comparison of the amount received with the control Note, AAA - bits can Accept any value from 000 to 111. 0/1 - the zero value corresponds to the younger device, the one - to the senior device. Table 2 Continued table. one Signature analyzer with comparison of obtained and control signatures Signature Analyzer Oh oh 1 1 about 1 1 about 1 about 1 about 1 about 1 oh oh oh oh oh 1 Table 3 about about about about 1 1 1 oh oh oh 1 1 1 1 about about 1 1 1 1 1 about o 1 1 1 1 i 1 about 1 1 1 1 1 1 1 about 1 1 1 1 1 1 1 five Editor A. Ogar Compiled by A.Sirotska Tehred I. Popbvich Proof-reader V. But ha 2966/52 Circulation 672 Subscription VNISHI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, 4/5 Production and printing company, Uzhgorod, st. Proty Ktna, 4