SU1315987A1 - Interface for linking electronic computers - Google Patents

Abstract

The invention relates to computing and can be used in two-machine complexes, for example, to interface high-performance computers with micro-computers. The aim of the invention is to expand the class of tasks of the device by providing control of the information path of the auxiliary computer (VM2). The invention makes it possible to verify the information path of the information of the auxiliary computer. In this case, VM 2 carries out a check of both the adapter 3 itself and cable information communication lines. The latter is achieved by introducing the interface switching unit 4, which contains the second electrical parameter matching node 12, register 13, transceiver 14. When the device is in Control mode, VM 2 writes information register 11 and register 13 information that is read and converted to logic levels signals of interacting computers and received by VM 2. VM 2, based on the analysis of the transmitted and received information, concludes that the information chain is operational. At the same time, for the most complete verification of the informational tract, unit 4 can be located in close proximity to the main machine. 1 hp f-ly, 6 ill., 1 tab. 57 i (L yr: 00 cl 00

Description

1.1

The invention relates to computing and can be used in computing systems for interfacing large high-performance computers with microcomputers (for example, BESM-6 and Electronics-60).

The aim of the invention is to expand the class of tasks of the device by providing control of the information path of the auxiliary computer.

FIG. 1 is a block diagram of the device; in fig. 2-4 are functional diagrams of a control unit, an output switch and a control switch; in fig. 5 and 6 - timing charts of the device.

The device contains (Fig. 1) main 1 and auxiliary 2 computers (VM1 and VM2), adapter 3, block 4 of the switching interface signals. Adapter 3 consists of a first electrical parameter matching node 5, a control unit 6, an output switch 7, an output readiness trigger 8, a control switch 9, an input readiness trigger 10, and an information register 11. The interface switching unit 4 comprises a second electrical parameters matching node 12, register 13 and transceiver 14.

The control unit 6 (Fig. 2) comprises an address switch 15, a status register 16 j interrupt vector address encoder 17, interrupt trigger 18, channel transmitter group t9, control signal decoder 20. The address switch 15 consists of the HE elements 21, the contact sockets 22, the NAND element 23 and the trigger 24. The address vector encoder 17 consists of the input interrupt demand trigger 25, the output interrupt demand trigger 2b, the delay element 27, and NOT 28 and 29, the interrupt request trigger 30, the AND 31 and AND-NOT 32 elements and the interrupt vector address switch 33.

The decoder 20 control signals contains a trigger (register) of 34 lower bits, a decoder 35, an AND-HE element 36, a delay element 37, an AND-HE elements 38 and 39, and an AND 40 element

The output switch 7 (Fig. 3) contains the main trunk groups; the switches 41 and 42 and the channel group

72

transceivers 43. The switch 9 of control (Fig. 4) contains a group of elements AND NOT 44 and 45.

The device also contains tires

(lines) 46-95 communications between the blocks and elements of the device.

Tires 46, 47 and 48, 49 connect the device to the first (main) VM 1, and tires 50-52 to the second

(auxiliary) VM 2, information bus 56 of which is connected to the address input of block 6 and information inputs of register 11 and trigger 8. Tires 53-55 denote the first to third,

information inputs, and buses 57 and 58 - the second and third information outputs of the output switch 7. Lines 59, 67-70 and 73 form the bus 54 of the second information input of the switch 7, and lines 60, 71 and 72 form the group of control inputs of the switch 7.

Input readiness trigger 10 serves to receive a write read input signal and to indicate

Readiness VM2 input information. Bus 67 is used to transmit an interrupt signal to VM 1, bus 64 is an indication of the mode of interruption of the program VM 1, bus 65 is a signal to read bits

the status register 16, the bus 66, the output signals of the state register 16, and the band 77, the output signals of the interrupt vector address.

The switch 4 of the interface is designed to organize the operation of the device in the diagnostics mode of the information path of VM 1 and 2.

Signals Input, Output, Synchronization (SIL), Interrupt Provision (IDR) signals from VM 2 are sent via lines 79-82 from block 2. From the output of switch 15, the signal is selected. The device goes through line 83 to the input of decoder 20, which is via line 84

Gates recording information bits of the register 16 of the state and readiness of the trigger 10, and on line 85 gates the interrupt trigger 18 to detect the interrupt signal of VM 1.

The table describes the functions of the decoder 35.

Functionality

Record of status bits

Table continuation

Perform function

Record the interrupt request for VM 1, write register information 11

Writing information to the registers 11 13

Read data when working in the readiness survey mode

Reading the status register bits

Trigger 8 readiness output data-. This is used to indicate the availability of information transmitted by VM 1 and VM 2 via bus 55. At the initial moment, trigger 8 is in the state O.

The readiness trigger 10 data input serves to indicate that the VM 2 is ready to exchange information fO between the computers in the ready polling mode. At the initial time, trigger 10 is in state O.

The node 12 for matching electrical parameters of block 4 (Fig. 5) 15 is intended for matching electrical (logical parameters of logic 0 and logic 1 VM 2 and VM 1).

FIG. 6 shows timing diagrams of the execution of the cycle Output, with more than 20 in FIG. 6a shows the signals on the device bus 50, FIG. 66 is a SIL signal on line 81; FIG. 6b - Signal Output on line 80, in FIG. 6d is a signal on line 60, .25 on FIG. 6d - SIP signal at the output of the decoder 20 (line 92). FIG. 7 shows the timing of the execution of the Entry cycle (the timing for all the cycles are the same), 30 with FIG. 7a shows the signals. on bus 50, in FIG. 76 - signal SIL on line 81, in FIG. 7c - signal

  . on line 79, in FIG. 7d - sig n - nal on one of lines 93-95 of three post. The switch 33 serves to install, ,,,.

“Es the last outputs of the decoder 35, on

interrupts for the address of the interrupt vector. AT- - , ", ,,,

 - .. Fig. 7d - SIP signal on line 68.

initial moment trigger 25

is in state O, and the trigger 26 is in 1. Interrupt trigger 18 is designed to generate interrupt signals of VM 1, at the initial moment of time trigger 18 is in state O.

Node 5 matching electrical .parameters serves to align

Reading information at cycle I

Reading information at cycle II

Reading information at cycle III

40

45

Cycles Output, three cycles Input is needed to diagnose faults of adapter 3 and cable lines and is carried out before the start of the working exchange of VM 1 and VM 2. These cycles are not necessary during the work of VM 1 and VM 2, and only allow release a large machine (VM 1) from unusual operations.

the electrical parameters of the logical 0 and the logical 1 polarity and level at the junction with VM 1. From the outputs of switch 7, lines 86-91 of bus 57 (Fig. 3) are formed: a read signal of diagnostic information when checking bus 47 (line 86), the diagnostic information reading signal during bus 47 check (line 87), the diagnostic information recording signal in

45

50

Cycles Output, three cycles Input is required for diagnostics of malfunctions of adapter 3 and cable lines and is carried out before the start of the working exchange of VM 1 and VM 2. These cycle are not necessary during the operation of VM 1 and VM 2, and they only allow the release of a large machine (VM 1 from unusual operations.

Block 4 is located in close proximity to the computer. This ensures that cable lines are checked along their entire length.

The device works as follows.

The exchange of information between computers is carried out in software mode.

register 13 (line 88), readiness data signal (only for the main ones are entered (line 89), signal data are output (line 90), signal is input input to VM 2 (line 91).

BM 1), or by interrupt m (for both). The device has a control mode VM 2.

Cycles Output, three cycles Input is needed to diagnose faults of adapter 3 and cable lines and is carried out before the start of the working exchange of VM 1 and VM 2. These cycles are not necessary during the work of VM 1 and VM 2, and only allow release a large machine (VM 1) from unusual operations.

Block 4 is located in close proximity to the computer. This ensures that cable lines are checked along their entire length.

The device works as follows.

The exchange of information between computers is carried out programmatically in the readiness survey mode (only for the main

sa readiness (only for main

BM 1), or by interrupt m (for both). The device has a control mode VM 2.

five

In the Monitoring mode, a complete autonomous check of the adapter 3 and cable lines of VM 2 is performed. This mode is carried out with the help of channel cycles Output and Input of VM 2 (Fig. 5. And 6). VM 2 in the address part of the cycle Output sends the channel address word over bus 50. The word comes through the output switch 7 via bus 56 to the inputs of the state register 16, the address switch 15, the decoder 20. The address bits of the address word are written to the address assigned to VM 1, VM 1 address is set at the design stage of the two-machine Complex and is formed by sealing the jumpers in slot 22, If the addresses at the output of the NAND 23 element coincide, a signal appears. The device is selected, which sets the trigger 24, After setting the address word VM 2 via control, it generates bus 51;. the signal SIL, arriving via line 81 to the inputs of the flip-flops 24 and 34, and recording information located on their information inputs. Then, VM 2 removes the address word, places diagnostic data on bus 50, and sends a signal via control bus 51, which is fed via line 80 to the input of decoder 35,

Diagnostic data from the output of the transceiver 43 through the register 11 and the transmitter 41 are transmitted by bus 58 to the input of register 13. In accordance with the code written in the lower bits of the address word, signals appear at the third output of the decoder 35 and lines 61 and 68 which write diagnostic data to the registers 11 and 13, the signal from the third output of the decoder 35 also goes to the NE-36 element and from its output through the delay element 37 to the input of the channel transmitter 19, which forms the CIP signal, VM 2, receiving the CIP signal , removes the signal output, mouth copulating data signal and the IAM,

Further, VM 2 performs three Input cycles, during which various interface blocks are monitored.

In this case, on the basis of the transmitted and received information, VM 2 concludes that the information chain is operational.

First cycle Bus 50, output switch 7, information register 11, switch 9 control 159876 are being tested.

l, VM2 in the address part of the cycle transmits through the bus 50 the address word of the channel and via line 81 the signal of the SIA arriving at the inputs of the flip-flops 24 and 34 and

After recording information, VM 2 removes the address word. and generates on line 79 a signal input to the input of the decoder 35, and on line 93 of the sixth I of the decoder 35 there appears a signal coming through line 63 to the input of switch 9 and allowing the passage of diagnostic data through the elements of IS 44 tires 58

15 of the switch 7 to the channel VM 2. Simultaneously, the signal t of line 93 through the element IS-HE 36, the delay element 25 is fed to the input of the transmitter 19, which on the bus 52 generates an SIP signal

20 indicating that the data is placed in the channel VM2. VM2 receives a CIP signal, data, removes Signals Input, SIA (on lines 79 and 81), completing feM with the most channel cycle

25 Enter,

Second cycle. Information bus 58 is being tested. In this case, the code written in the lower bits of the address word corresponds to the seventh output 30 of the decoder 35, the control signal from the seventh output of the latter on line 69 opens the transmitter 41 and the transceiver 14, the transceiver 14 changes the direction of transmission information, and diagnostic data from the output of the register 13 through the transceiver 14, the bus 58, the elements of the AND-44 of the switch 9 are fed to the channel VM 2 via the bus 76.

40 Third cycle. Information bus 58, node 5, output switch 7 is being tested. In this case, the code written in the lower bits of the address word corresponds to the eighth output

45 of the decoder 35, the Control signal from the eighth output of the latter through line 95 through element 40 and lines 60 and 70 is fed to the inputs of transceiver 43 and node 12, Transmitter 50, sensor 43 changes the direction of information transfer, and diagnostic. data from the output of the register 13 through the node 12 matching, the bus 47, the node 5 and the bus 55 of the switch 7 arrive

55 channel VM2,

In the readiness survey mode, VM 1 operates as follows.

VM2 in case of readiness for information exchange in the polling mode ready713

during the channel cycle, the Output has set trigger 10 to state 1. At the same time, the read word write signal of the address word excites line 84 of the first output of the decoder 35. The VM 1 control program analyzes the state of the bus 57, namely the readiness circuit, and the trigger 10 in state 1 exposes an information word on bus 47 and transmits a signal over bus 46. The data is set. The last one on line 71 sets the trigger 8 to state 1, and a signal appears on bus 57 | C on line 89. Data entered is input to VM 1. VM 2 via a channel cycle Input polls the state of the first output bus 75 of switch 9 control In this case, if trigger 8 is in state 1, i.e. on bus 55 there is information, VM 2 makes its input: on line 60 from the fourth output of decoder 35 a signal appears that puts the information into channel VM 2, trigger 8 is set to the initial state O and VM 1 on the trailing edge of the data. line 89) removes the information word. The following processes are repeated.

In the interrupt information exchange mode, the device operates in the following way.

The initiator of the exchange of the vehicle (VM2). This exchange mode is for it the only information transfer mode. The exchange occurs with the help of the channel cycle Output, discussed earlier. But at the same time, the code transmitted in the lower bits of the address word corresponds to the second output of the decoder 35. When the signal appears at the second output of the last, information is recorded in the register 11 and the interrupt trigger 18 is set to state 1. At the same time, on line 90 of adapter 3 A program termination signal appears. The data is outputted to the VM 1. VM 1, having received the interrupt signal, receives the data transmitted by VM 2 and transmits on line 72 the received data signal, which sets the trigger 18 to the initial state O.

The initiator of the exchange is the main machine (VM 1). In VM 2, a vector interrupt system is adopted. Address vector Pre59878

jerking upon receipt of the requirement to enter or output information is different and recorded in the address switch 33. When operating in the interrupt mode of the VM 2 5 during the channel cycle Output, it writes to the register 16 the status codes allowing the VM 2 to enter or output information in the interrupt mode. At the same time, the potential that allows or prohibits the operation of VM 2 in entering information arrives at the second input of the element ION 28 and the input to the second input of the element II NOT 29 enters information. VM 1 transmits the required 5-interruption to the output of information by the Data received signal, which is received via line 72, and through the element I-HE 29, trigger 30, element I-HE 32, channel transmitter 19 to 0 bus 52 of channel VM 2 VM 2 satisfied; This requirement generates an interrupt-assignment signal (RAD) on line 82, arriving at the inputs of the decoder 20 and the encoder 17, which resets the trigger 26 and the delay element 27 gates the trigger 30, which stores the information at its inputs. The address switch 33 places the vector address on buses 77 and 50 of channel 2 of VM 2.

At the same time, the signal R1P in the decoder 20 generates in the line 92 a response signal CIP, indicating that the address is placed in the channel. VM 2 receives the interrupt vector, removes the SPR signal and proceeds to service the interrupt subroutine for outputting information. Installation

  the trigger 26 to the initial state is produced by a response signal. The data is received when the first information word is transmitted.

When transferring information to VM 2

 According to the results, the device operates as follows.

VM 1 exposes the information word, i transmits a signal. Data is set. In this case, the trigger 8 and the trigger 25 are set to state 1. The signal from the output of the trigger 25 through the element AND-HE 28, the trigger 30, element AND-HE 32 and the channel transmitter T9 enters the channel VM 2, causing

 program interruption requirement.

Further, the considered processes are repeated, but at the same time, an interrupt vector for entering information is formed.

Claims (2)

1. A device for interfacing two computers, comprising a control unit, an output switch, a control switch, an output readiness trigger, an input readiness trigger, an information register and the first electrical matching node and the input readiness trigger are connected to the fourth and fifth outputs of the control unit, respectively. This is because, in order to expand the class of tasks of the device, the interface signal switching unit is inserted from the register of the second electrical parameter matching node 20 parameters, the first and second inputs of the boxes and the transceiver, the second information input and the control input of the control switch are connected respectively to the third information output of the output switch 5 and the sixth output of the control unit, the third output and the third group of outputs are connected respectively to a group of control inputs and the second information input of the output switch, the third information input connected to the second output of the first node to match the electrical parameters, and the second m data output - to 25 iy- formational input register and input-output transceiver, control inputs of which the first and second electric parameters matching node input connected to the second output of the output switch Bb | GHOD |. the register is connected to the information input of the transceiver, the second input of the second electrical parameter matching node, the output of the first electrical electric parameter matching terminal 35 connected to the second input. transceiver output is the output of the device for connecting the information input of the first Secondly, they are the corresponding inputs of the device for connecting the control and information outputs of the first computing machine, the first group of outputs of the first electrical parameter matching node is connected to the group of control inputs of the output switch, the first group of synchronization inputs of the control unit of the output, the first output and the second group of synchronization inputs of the control unit exchange are the corresponding output and input of the device for connecting the input The interrupt request and the synchronization output of the second computer, the second output of the control unit, the first and second information outputs of the control switch and the information input / output of the output switch form the input-output of the device for connecting the information input / output of the second computer, the first information input of the output switch is connected with the output of the information register, and the first information output - with the information inputs of information registrar register and trigger ready-computing machine. These inputs and the address input of the control unit, the third output of which is connected to the reset input of the output ready trigger, the direct outputs of the output and input readiness trigger and the first group of outputs of the control unit are connected to the first information input of the control switch, the inverse output of the output ready trigger 2. A device according to claim 1, characterized in that the control unit comprises a control decoder; signal, address switch, interrupt vector address coder, channel transmitter group, status register and interrupt trigger, the first and second outputs of the decoder control signals connecting Yes, the direct output of the ready availability trigger -50 is respectively with the synchronous input of the drive and the second group of outputs of the control unit are connected to the second information input of the output switch, the second information output of which is the output of the device for connecting the control input of the first computer, the synchronous inputs of the information register the status switches and the reset input of the interrupt trigger, the direct output of which and the third output of the control signal decoder form the second 55 group of block outputs, the information inputs of the status register and the address switch are connected to the block address input and information input 1315987 ten and the input readiness trigger are connected to the fourth and fifth outputs of the control unit, respectively. It is due to the fact that, in order to expand the class of tasks of the device, the interface signal switching unit entered from the register of the second electrical parameter matching node and a transceiver, the second information input and the control input of the control switch are connected respectively to the third information output of the output switch and the sixth output of the control unit, the third output and the third the group of outputs of which are connected respectively to the group of control inputs and the second information input of the output switch, the third information input connected to the second output of the first node of the electrical parameters matching, and the second information output to the information input of the register and the input-output of the transceiver Their inputs and the first input of the second electrical parameter matching node are connected to the second output of the output switch, VL | GKT |. the register is connected to the information input of the transceiver, the second input of the second electrical parameter matching node, the output connected to the second input of the first electrical parameter matching node-. transceiver output is the output of the device for connecting the information input of the first 2. The device according to claim 1, characterized in that the control unit contains a control decoder; These signals, the address switch, the address encoder of the interrupt vector, the group of channel transmitters, the status register and the interrupt trigger, the first and second outputs of the decoder control signals being connected. -50 are respectively with the synchronous input of the status register and the reset input of the interrupt trigger, the direct output of which and the third output of the control decoder form the second 55 group of outputs of the block, the information inputs of the status register and the address switch are connected to the address input of the block and the information input control signal decoder, the fourth and first outputs of which are the third and fourth block exchange outputs, the fifth output of the decoder of the control signals, the output of the status register and the inverted output of the interrupt trigger form the first output block of the block, the sixth output of the decoder the control signals are the sixth fO output of the block, and the seventh and eighth outputs form the third group of outputs of the block, the first, second and third information inputs of the interrupt vector address encoder are connected respectively / 5 with the output of the state register and the first group of synchronization inputs of the exchange block, and the synchronized input with the second group of synchronization inputs of the synchronization inputs the control signal encoder and the address switch are connected to the second group of synchronization inputs of the block, the output of the address switch is connected to the control input of the decoder of the control signals, the ninth output of which is the output of the block state, and the tenth output is connected to the input the first channel transmitter of the group, the setup input of the interrupt trigger is connected to the first group of synchronization inputs of the block exchange, the first output of the interrupt vector address encoder is the second output of the block, and the second second output - to an input of the second channel of the transmitter group, the outputs of the first and second channel transmitters group obrazuyut- first output unit. shhhh j needles  Address V Porey II Data b b Z d Phage. five Editor V.Danko ig. 6 Compiled by V. Vertlib Tehred M. Khodanych Proofreader G. Reshetnik Order 2364/51 Circulation 672 Subscription VNIRPShch State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, 4/5 Production and printing company, Uzhgorod, st. Project, 4