JPS6027054B2 - Input/output control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input/output control scheme that uses adapters to extend a bus interface.

Generally, when extending a bus interface that connects multiple input/output devices to a central processing unit, an adapter is used due to physical and electrical limitations. is connected, and the second bus interface is output from this adapter. This adapter only corrects the timing of the bus interface signals and relays the signals, so when a fault occurs on the bus interface, the central processing unit can locate the fault by connecting it to the first bus interface, adapter, and There was a problem in that it was impossible to specify which part of the second bus interface it was and it was impossible to isolate it. Therefore, an object of the present invention is to provide a system comprising a central processing unit, a first bus interface, an adapter, and a second bus interface, in particular an input/output device connected to the second bus interface and a central processing unit. When a failure occurs on the bus interface during the transfer of input/output command input/output data, etc. between There is a particular thing.

In the present invention, whereas conventional adapters only correct the timing of interface signals and relay signals, the present invention receives test output data from the central processing unit via the first bus interface. Then, the received test output data is returned and transmitted to the central processing unit via the first bus interface, so that the central processing unit performs a comparison test between the test output data and the returned data. When a fault occurs on a bus interface, it is possible to test the health of the first bus interface or adapter, and therefore to identify the location of the fault on the first bus interface, adapter, or other adapter. It is now possible to specify which of the second bus interfaces it is.

In the present invention, the adapter is connected as one of the input/output devices of the first bus interface in order to receive test output data at the adapter and transmit the received test data back as described above. ing.

That is, the adapter has a unique input/output device address that can be specified by the central processing unit as an input/output device connected to the first bus interface, and receives and processes input/output commands, input/output data, etc. from the central processing unit. have a function.

For example, when the central processing unit specifies an adapter-specific input/output device address and an input/output command specifies that the adapter is output data for testing, the adapter outputs the output data from the central processing unit. Store data in wrap register. Next, when the central processing unit specifies the adapter's unique input/output device address and specifies that the input/output command is to read test data, Agupta transfers the data stored in the loopback register to the central processing unit. The test data is transmitted to the equipment, allowing the central processing unit to compare the test data. An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a system according to the present invention, in which 1 is a central processing unit, 2 is a first bus interface, 3 is an adapter, 4 is a second bus interface, and 5 and 6 are the first bus interfaces. an input/output device connected to interface 2,
7 and 8 are input/output devices connected to the second bus interface.

FIG. 2 shows a detailed circuit diagram of the adapter 3, ]0,11
, 12, 13 and 14 are signals constituting the first bus interface 2, 10 is an input/output device address signal, 11 is an input/output command signal, and 13 is an output from the central processing unit to the input/output device. data signal, 12 is an output strobe signal indicating that valid information is set in the input/output device address signal 10, input/output command signal 11, and output data signal 13; 14 is a central processing signal from the input/output device; is the input data signal to the device.

Further, signals 20, 21, 22, 23, and 24' constitute the second bus interface 4, and include an input/output device address signal 10, an input/output command signal 11, an output strobe signal 12, and an output data signal 13, respectively. , corresponds to the input data signal 14. Furthermore, 30, 31, 32, 33
is a non-inverting gate which receives the signals 10, 11, 12, 13 of the first bus interface 2 and receives the signals 34, 35, 36.
, 37 are non-inverting gates which output the signals 20, 21, 22, 23 of the second bus interface 4. Also,
38 is a negation gate, 39, 40, 44 and 45 are AN
D gate, 41 is an OR gate, 42 is an input/output device address decoder, 43 is an input/output command decoder, 46
is a wrap register. In the figure, except when performing the fault isolation function, the adapter 3 is
It performs only the function of connecting the first bus interface 2 and the second bus interface 4.

That is, the input/output device address signal 10 does not specify an input/output device address specific to the adapter 3, and therefore the output of the input/output device address decoder 42 becomes ``0''.
Since the outputs of the AND gates 44 and 46 are set to "0", the output of the AND gate 40 becomes "0", and the output of the NOT gate 38 becomes "1".This inhibits the operation of the loopback register 46. and AND gate 3
9 and OR gate 41 transfer input data signal 24 to input data signal 14. Further, the signals 10, 1 1, 12, 13 of the first bus interface 2 are transmitted by non-inverting gates 30 and 34, 31 and 35, 32 and 36, 33 and 37, and the signals of the second bus interface 4 It is output as 20, 21, 22, 23. On the other hand, when performing the fault isolation function, the input/output device address signal 10 specifies an input/output device address unique to the adapter 3.

First, when outputting test output data from the central processing unit 1 to the adapter 3, writing to the return register 46 is specified in the input/output command signal 11, and the test output data is set in the output data signal 113. Been,
An output strobe signal 12 is output. As a result, the output 100 of the input/output device address decoder 42 and the input/output command decoder 43 becomes "1", and the AND gate 44
Accordingly, at the timing of the output strobe signal 12 transmitted through the non-inverting gate 32, the non-inverting gate 33
The return register 46 is instructed to take in the output data signal 13 received via the return register 46. Next, in order to return and transmit the output data received and stored in the return register 46 to the central processing unit 1, the input/output command signal 11 is instructed to read the return register 46.

As a result, the output of the input/output device address decoder 42 and the output 101 of the input/output command decoder 443 are “
1", the output of the AND gate 45 is set to "1", the output of the NOT gate 38 is set to "0", and the AND gate 39 prohibits the input data signal 24 from being transmitted to the input data signal 14. AND gate 40, OR
The output of the folding register 46 is transmitted to the input data signal 14 by the gate 41. As explained above,
According to the present invention, when a failure regarding the bus interface occurs, the second bus interface extended by the adapter is disconnected, and the test data is transferred from the central processing unit between the first bus interface and the adapter. is transmitted back and the central processing unit connects the first bus interface, without removing the adapter, etc.
It becomes possible to isolate where the failure is occurring in the adapter or the second bus interface.

[Brief explanation of the drawing]

FIG. 1 is an example of a configuration diagram of a system to which the present invention is applied.
FIG. 2 shows an example of a detailed circuit diagram of the adapter. 42...Address decoder, 43...I/O command decoder, 46...Return register. Oh figure 2 figure

Claims (1)

[Claims] 1. A central processing unit, a first bus interface, an adapter connected to the first bus interface as one of the input/output devices, and one or more input/output devices connected to the adapter. In the system configured by a second bus interface, the adapter may include means for receiving output data from the central processing unit, and means for transmitting the received output data back to the central processing unit. This is an input/output control method that improves the ability to isolate faults. 2. The adapter has an input/output device address unique to its own device, has address detection means for detecting that its own address has been specified, and command detection means for detecting an input/output command instructing return, and outputs of these detection means. 2. The input/output control method according to claim 1, wherein the output data is transferred back according to the following.