JPH0376352A - Simulating test equipment - Google Patents

Abstract

PURPOSE:To considerably reduce a test man-hour by receiving a command to an input and output device in a data transfer device, reading sequentially a test command group stored in a main storage device and executing the command. CONSTITUTION:A data control word is received by a command reception circuit 56, and the signal is sent to a test mode control circuit 58, then the circuit 58 gives a command to a test command readout control circuit 57 again to read a test command group 21 stored in a main storage device 2 and gives it to an input and output processor 3 as an interrupt signal via s selector 59 or the like similarly to the preceding case. The processor 3 transfers the data from an address designated by the main storage device 2 to a transmission buffer 51. A channel control circuit 50 allows a transmission buffer 51 to receive the transfer data while making transmission reception of a control signal with the circuit 58, sends the data to a selector 52, a transmission register 53 and a driver DR, where the data is aborted. The circuit 58 causes a simulating fault to an optionally designated circuit in a channel device 5 by using a simulating fault generation command data stored in the circuit 58, an error is detected in the circuit 50 and the transfer is finished.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to a data transfer device. In particular, the present invention relates to a data transfer device that allows a host device to test its own device without connecting a lower device to the data transfer device.

〔overview〕

The present invention is a method for testing a data transfer device from a host device without connecting a lower device to the data transfer device, and reduces testing man-hours by generating a false failure in the data transfer device and checking this condition. It is designed to make it possible to achieve the following.

[Conventional technology]

BACKGROUND ART Conventionally, a data transfer device is tested by connecting an input/output device or a tester that transfers data to the data transfer device. In addition, a data return means is provided in the data transfer device to test the data bus.

[Problem that the invention seeks to solve]

However, depending on the scale of the information processing system, a processor dedicated to input/output may be connected to the system bus connected to the main memory, and hundreds of data transfer devices and input/output devices connected to this may be connected below this processor. may be provided. When manufacturing such a system, conducting a test by connecting all the input/output devices and testers of the data transfer device has the drawback of requiring a large amount of expense and floor space for test preparation. In addition, when tests are performed by connecting input/output devices, etc., and a fault is detected, it is difficult to determine whether the fault is on the data transfer device side or the input/output device side; It is necessary to perform a test by replacing the equipment or tester, and this requires the complication of stopping the system, turning off the power, and changing the cable connections. In addition, when testing a data bus by looping back data, a command is issued each time with the host device in mind that it is in test mode, so there is a drawback that it is not possible to test a series of operation sequences.

The present invention eliminates such drawbacks by keeping the input/output device in a blocked state, turning the data transfer device into a loopback state, and executing commands from the host device and internally stored commands. By connecting the input/output device, the data transfer device can be operated and tested as if a series of operation sequences are being performed with the input/output device via the data transfer device, and a false failure can occur at any timing in the command sequence. The purpose of the present invention is to provide a data transfer device that can perform the following functions.

[Means for solving problems]

The present invention provides a pseudo test device that is inserted into a path between a higher-level device and a lower-level device and is related to a data transmission device that includes a channel device, in which a plurality of test commands and the occurrence of a pseudo failure corresponding to each of the test commands are provided. a storage area for storing data; and a test mode control means for issuing an instruction to block a path between the data transmission device and the lower-order device in response to an instruction indicating a test mode given from the higher-order device; Checking for blockage of the path between the data transmission device and the lower-level device, sequentially reading out the test commands stored in the storage area, analyzing the read test commands, and executing them on the channel device. A test command read control circuit, and a pseudo fault occurrence control circuit that causes the channel device to generate a pseudo fault indicated by pseudo fault occurrence data corresponding to the test command read when the test command read control circuit reads out the test command read control circuit. It is characterized by:

[Effect]

Receive commands for peripheral devices sent from the host device. When a test mode instruction is given from the host device,
Gives an occlusion signal to peripheral devices. A group of test commands stored in the main memory is read out sequentially from the first address given by the host device, analyzed, and then executed. A group of commands and corresponding pseudo fault occurrence instruction data are provided in the main storage device, and are read out along with the commands to control the occurrence of a pseudo fault.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of this embodiment, in which the data transfer device is a channel device connected to an input/output processor. As shown in FIG. 1, a main processor 1, a main storage device 2, a turnout processor 3, and a diagnostic processor 4 are connected to the system bus, and a plurality of channel devices 5 are connected to the input/output processor 3. An input/output device 7 is connected to each of the devices 5 via a human output control device 6 . The channel device 5 includes a conventionally provided channel control circuit 50, a transmission buffer 51 of the same byte width as the system bus width, and a transmission buffer 5.
1, a 1-byte transmission register 53 connected to the selector 52, and a 1-byte transmission register 53 connected to the selector 52.
A 1-byte driver DR that sends the contents of the data to the data transfer line between it and the input/output control device 6, a 1-byte receiver RE connected to this data transmission/reception line, and a 1-byte receiver 1 that receives the output from the receiver RE. It has a byte reception register 55 and a reception buffer 54 that stores and outputs the contents of the reception register 55 by bytes equal to the system bus width, and commands that are newly input to the transmission buffer 51 in parallel and transmitted. a command receiving circuit 56 that receives the test commands; a test command read control circuit 57 that sequentially reads out the test command group 21 stored in the main memory 2 and executes it after analysis;
The artificial fault occurrence control circuit 5A reads out the pseudo fault occurrence instruction data 22 stored in the main storage device 2 in response to the read command and controls the occurrence of a pseudo fault, and the human output line of the channel control circuit 50 is connected in parallel. The test mode control circuit 58 is connected to the receiver RE, and the receiver R is provided between the receiver RE and the reception register 55 according to the control of the test mode control circuit 58.
A selector 59 that switches between the output of E and the output from the test command read control circuit 57 and outputs it to the reception register 55.
and has.

Note that the channel control circuit 50 ignores two signals, the test mode designation signal and the test mode release signal, which are applied via the input/output processor 3, but all other control signals and controls are ignored even during the test mode. Execute. Also,
The test mode control circuit 58 receives two signals, a test mode designation signal and a test mode release signal, from the input/output processor 3, and sends a blockage signal ( For example, it sends a low level>, executes the received command of the channel control circuit 56 on behalf of the input/output control device 6, and reads the command to be sent from the input/output control device 6 to the input/output processor 3 from the main storage device 2. , from the test command read control circuit 57 to the selector 5
9 or reads out the pseudo-fault occurrence instruction data 22 from the main storage device 2, and performs an operation to generate a preset pseudo-fault during normal operation.

That is, this embodiment shows a main storage device 2 which is a storage area for storing a plurality of test commands and pseudo-failure occurrence data corresponding to each of the test commands, and a test mode given from a host device. A test mode control circuit 58, which is a test mode control means that issues an instruction to block the path between the data transmission device and the lower device in response to an instruction, and a test mode control circuit 58 that closes the path between the data transmission device and the lower device. a test command read control circuit 57 which sequentially reads out the test commands stored in the storage area, analyzes the read test commands, and executes the read test commands to the channel device included in the data transmission device; ,
The present invention is characterized by comprising a pseudo-failure generation control circuit 5A that causes the channel device to generate a pseudo-failure indicated by the pseudo-failure generation data corresponding to the test command read when the test command read control circuit 57 reads out the test command. .

Figure 2 is a sequence diagram showing the data transfer operation in the test mode, and the dotted lines between the channel device and the input/output device (including the input/output control device) indicate data transmission and reception when not in the test mode. The operation of this embodiment will be described below with reference to FIG.

First, when the test mode is specified by specifying the address of the channel device 5 from the main processor 1 or diagnostic processor 4, the input/output processor 1 receives this information and sends a control signal line to the channel device 5 at the specified address. Specify the test mode via

In response to this designation, the test mode control circuit 58 sends a closure signal to the human output control device 6 to open all connection lines with the channel device 5. Next, main processor 1
Alternatively, the diagnostic processor 4 gives a data transfer instruction to the input/output processor 3. Therefore, the input/output processor 3 learns the address of the designated channel device 5 from the designated control information in the main storage device 2, and sends an activation signal to this channel device 5. This activation signal is sent to the channel control circuit 50.
However, the input/output control circuit 6 cannot receive it, and the test mode control circuit 58 receives it instead. When the test mode control circuit 58 receives the activation signal, it instructs the test command read control circuit 57 to read test commands from the main memory 2 based on the starting address of the test command group 21 given in advance from the host device. is read out, and this command is given to the turnout processor 3 as an interrupt signal via the selector 59, reception register 55, and reception/< buffer 54. Subsequently, the test mode control circuit 58 instructs the simulated fault occurrence control circuit 5A to read the simulated fault occurrence instruction data 22 corresponding to the read test command group 21 from the main storage device 2, and the test mode control circuit 58 hold within. Therefore, the input/output processor 3 again uses the normal procedure to transmit a data control word containing information such as transmission/reception designation, address and count of transfer data in the main memory 2 from the specified control information in the main memory 2. . This data control word is received by the command receiving circuit 56, and when this signal is transmitted to the test mode control circuit 58, the test mode control circuit 58 again instructs the test command read control circuit 57 to store it in the main memory 2. The test command group 21 is read out and is given as an interrupt signal to the input/output processor 3 via the selector 59 etc. as in the previous time. As a result, the turnout processor 3 transfers the data from the designated address of the main storage device 2 to the transmission buffer 51 in the normal procedure. At this time, the channel control circuit 50 sends and receives control signals to and from the test mode control circuit 58, causes the transmission buffer 51 to receive the transfer data, and transfers the received data to the selector 52, the transmission register 53, and the driver DR.
to be disposed of. Here, test mode control circuit 5
If there is an instruction to generate a pseudo fault based on the pseudo fault occurrence instruction data stored in the channel device 8, the test mode control circuit 58 can cause a pseudo fault to occur in an arbitrarily designated circuit within the channel device 5. As a result, an error is detected in the channel control circuit 50, and the transfer ends. The test mode control circuit 58 instructs the test command read control circuit 57 to send an end status request command, which is received by the channel control circuit 50 via the control line. After receiving all the confirmation signals, the test command reading control circuit 57 is again instructed, and the end status and end command are sent to the selector 59 as before.
The data is sent to the input/output processor 3 via the above, and the series of operations is completed.

Note that the data transfer described above is for transmission to the input/output device 7, but in the reception test, specific data may be stored in the main storage device 2 in advance and then sent.
Return information is included in the data control word, and the test mode control circuit 58 that receives this return information transmits the data received by the transmission buffer 51 to the driver DR and the register/register.
(The data may be stored in the reception buffer 54 via the RE and sent back by instructing the channel control circuit 50.

In this embodiment, commands are sent and received between the input/output processor 3 and the channel device 5 via the data bus, but if these commands are sent via the control line, the command reception The circuit 56, the test command read control circuit 57, and the pseudo fault occurrence control circuit 5A are all connected in parallel to the control line between the input/output processor 3.

〔Effect of the invention〕

As explained above, the present invention receives commands to an input/output device in a data transfer device, sequentially reads out a group of test commands stored in a waist storage device, executes these commands, and performs input/output as if it were input/output. It is possible to connect the device and perform a series of operation sequences with the input/output device, and also to read pseudo failure occurrence instruction data stored in the main memory in response to test commands. The failure detection means can be checked by generating a pseudo failure in the channel device, and the data transfer device can be tested without connecting input/output devices or test equipment to the data transfer device, resulting in a significant reduction in testing man-hours. There is.

[Brief explanation of drawings]

FIG. 1 shows block constituent countries showing the configuration of an embodiment of the present invention. FIG. 2 is a sequence diagram showing an example of a data transfer operation according to an embodiment of the present invention. l... Main processor, 2... Main storage device, 3...
Input/output processor, 4...Diagnostic processor, 5...
Channel device, 6... Input/output control device, 7... Input/output device, 21... Test command group, 22... Simulated fault occurrence instruction data, 50... Channel control device, 51.
...Send buffer, 52.59...Selector, 53.
...Transmission register, 54...Reception buffer, 55...
・Reception register, 56... Command reception circuit, 57.
...Test command read control circuit, 58...Test mode control circuit, 5A...False fault occurrence control circuit.

Claims (1)

[Scope of Claims] 1. In a pseudo test device related to a data transmission device including a channel device inserted in a path between a higher-level device and a lower-level device, a plurality of test commands correspond to each of the test commands. a storage area for storing pseudo-failure occurrence data, and a test mode control that issues an instruction to block a path between the data transmission device and the lower-level device in response to an instruction indicating a test mode given from the higher-level device; means, confirming that the path between the data transmission device and the lower-level device is blocked, sequentially reading out the test commands stored in the storage area, analyzing the read test commands, and transmitting the test commands to the channel device; a test command read control circuit that executes a test command read control circuit, and a pseudo fault generation control that causes the channel device to generate a pseudo fault indicated by pseudo fault occurrence data that corresponds to the test command that is read when the test command read control circuit reads out the test command read control circuit; A pseudo test device characterized by comprising a circuit.