KR900006530B1 - Method of and apparatus for diagnosing channel control unit - Google Patents

Abstract

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Description

[Name of invention]

Diagnostic method of channel control device and device

[Brief Description of Drawings]

1 is a main block diagram of a data processing system to which the present invention is applied.

2 is a view for explaining a connection state to a central control device of the channel control device according to the present invention.

3 is a block diagram of a channel control apparatus according to the present invention.

4 is a configuration diagram of a pseudo-input-output control device / doctor input-output device in a channel control device according to the present invention.

5 is a configuration diagram of an address selection circuit in the pseudo-input-output control device / pseudo-output device according to the present invention.

6 is a flow chart of the diagnostic method of the channel control apparatus according to the present invention.

Detailed description of the invention

(Technology)

The invention provides an input / output device via an input / output control device (magnetic tape control device, file control device, interface control device, etc.) connected to the common bus by a predetermined common bus interface control procedure by a command from the central control device. The present invention relates to a method and apparatus for diagnosing a controlling channel control device. In particular, a pseudo-input / output control device for simulating the operation of an input / output control device is installed in a channel control device to facilitate separation of an obstacle part and to improve diagnostic performance. A diagnostic method and apparatus for a channel control apparatus.

(Background)

The channel control device controls various input / output control devices via a common bus. For example, the central control device, the main memory device, and the channel control device are connected to the multibus, and the input / output control device is connected via the channel control device and the common bus. In a system in which an input / output device such as a printer or a magnetic tape device is connected to each input / output control device in series, the channel control device controls the input / output device via an input / output control device connected to a common bus by a command of the central control device. Then, data transfer control is performed in the program control mode or the direct memory access transfer mode. Here, the program control mode is to perform data transfer by controlling the input / output control device while the channel control device is connected with the central control device, and the direct memory access transfer mode is directly when the channel control device is connected with the main memory device. The main memory is accessed to perform data transfer.

When the central control unit detects a failure, a diagnosis is performed to detect which device has failed, and an input / output control device connected through a common bus from a channel control device has a configuration corresponding to various input / output devices. Therefore, since a diagnosis method and procedure corresponding to the configuration are required, a lot of test data for diagnosis has to be prepared and they have to be selected according to the type of input / output device.

In addition, in the case of a continuous failure state of the common bus due to a failure of the driver of the input / output control device connected to the common bus, it becomes impossible to perform diagnosis by operating the input / output control device.

As described above, since the conventional channel control apparatus includes only the data transmission circuit and the control circuit as main parts, there is a drawback that the diagnostic program is complicated by operating the input / output control apparatus to perform the diagnosis, and also through the common bus CB. It was very difficult to isolate the obstacle part of the apparatus connected in series.

(Initiation of invention)

An object of the present invention is to provide a pseudo-input / output control device capable of simulating the operation of the input / output control device in the channel control device to separate the plurality of different input / output control devices connected in series via a common bus from the channel control device. It is to provide a diagnosis method of whether a common bus interface of a channel control device is normal.

In addition, another object of the present invention is to provide a fault detection function in the channel control apparatus by causing the pseudo-input / output control apparatus to perform parity error data transmission and abnormal operation such as common bus timeout by the instruction of a program. It is to make a diagnosis.

In addition, another object is to provide a high speed diagnostic method of the common control unit, that is, the channel control apparatus of the plurality of input and output control apparatus and to improve the reliability of the system.

According to the present invention, by providing a pseudo-input / output control device and an input / output device capable of simulating the operation of different types of input / output control devices in the channel control device, it is possible to separate the obstacle portion of the channel control device and the input / output control device.

Moreover, the diagnosis of the channel controller is made possible regardless of the connected I / O controllers. Therefore, in the invention of the present invention, the repair time of the trouble can be shortened, and the independent diagnosis of the channel control apparatus can be performed, thereby providing an extremely economical diagnostic method.

(Best form for carrying out the invention)

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. 1 is a block diagram of a data processing system, in which 1, 1 'is a central control unit, 2, 2' is a main memory device, 3 ₀ to _{3 3} is a channel control device, 4 ₀ to 4 _{3 n} is an input / output control device, 5 _{0-5 3n} are an input / output device. In this figure, the central control unit 1, 1 'and the main memory unit 2, 2' have a fully symmetrical dual configuration.

That is, the central control unit 1 and the main memory unit 2 constitute a commercial accounting device, while the central control unit 1 'and the main memory unit 2' constitute a spare system.

The central control unit 1, 1 ', a main storage device 2, 2', the channel control unit _30-33 is connected to the multi-bus via the channel control unit _30-33 and the common bus input and output control unit 4 ₀ ~4 _3n In the data processing system in which the input / output devices 5 _{0 to} 5 _{3 n} such as a printer or a magnetic tape device are connected to each input / output controller 4 ₀ to 4 _{3 n} in series, in accordance with the command of the central control device 1, 1 ′. The channel control devices 3 ₀ to _{3 3} control the I / O devices 5 _{0 to} 5 _{3 n} via the I / O control devices 4 ₀ to 4 _{3 n} connected to the common bus, and perform data transfer in the program control mode or the direct memory access transfer mode. will be.

2 is an explanatory diagram of the connection between the central control unit 1, the main memory unit 2 and the channel control unit 3, and the channel control unit 3 includes a plurality of input / output controllers 4 ₀ , 4 ₁ ,. 4 _n are connected in series, and the following I / O control devices are not connected to the last I / O control device 4 _n , and the terminating resistor 6 is connected.

Each input / output controller 4 ₀ , 4 ₁ ,. 4 _n includes I / O devices 5 ₀ , 5 ₁ ,. 5 _n are connected, respectively. Channel controller 3 is connected to central controller 1 in program control mode 4 ₀ , 4 ₁ ,. Direct memory access in the state of being connected to main memory 2 except 4 _n . Data transfer is performed by directly accessing main memory 2 by the transfer mode.

FIG. 3 shows a specific example of the channel control apparatus 3 used in the present invention, where 7 is a data transmission circuit, which transmits and receives data, transmits and receives an address signal, and sends a clear signal through a common bus.

8 is a control circuit, which transmits and receives a control signal via a common bus.

9 is a pseudo-input / output control device for diagnosing the inside of the channel control device 3 and performing diagnostic-only pseudo-input / output control for diagnosing the interface between the central control device and the memory and the common bus interface.

Terminals a, b, c, d, and e are connected to the above-mentioned multiverse, and an address signal or a command of an input / output controller from the central controller 1, 1 'is transmitted to the terminal a, and the terminal b is connected to the terminal. Data from main memory is transferred.

From the terminal c, store data and address signals are sent to the main memory.

In addition, a control signal from the central processing unit is transmitted to the terminal d, and from the terminal e, various control signals are sent to the central processing unit.

Next, the common bus interface signal line inside the channel control apparatus will be described.

f (fp, fc) is a bidirectional data information line and includes a parity check bit line. g (gp, gc) is a bidirectional address information line, and also includes a signal line for an extended address.

h (hp, hc) is a signal when the interrupt request is accepted by the central control unit, address information sent by the central control unit to the device requesting the interrupt, system reset signal, or control of the common bus. It contains a response signal to the request to obtain a.

i (ip, ic) is a request signal for the I / O control device to obtain the bus control right, a signal for each I / O control device to interrupt the central control device, or a response signal indicating that the next bus control right is obtained or an interrupt permission is received. It includes a response signal.

j (jp, jc) is a signal for the central controller to specify the direction of information transmission, a signal for specifying whether the unit of information transmission is a word or a byte, or parity bit is valid for the input / output controller. Or a signal for requesting transmission or reception of information in the case of information transmission.

In addition, these common bus interfaces are generally performed in this type of data processing system in the related art.

The information lines k and l are newly installed in the present invention, k is a closed signal line for closing the pseudo-input and output control device 9, and l is a closed signal for closing the common bus.

That is, when this channel control device is used in a normal state (connected to a plurality of different types of input / output control devices via a common bus), the closed signal of the pseudo-input / output control device 9 is sent to k, and the pseudo-input-output control device 9 is separated from the various common bus interface lines. In the case of diagnosing the common bus interface of the channel control apparatus, a signal is given to the terminal d from the central processing unit based on the start of the diagnostic execution program of the central control unit. The common bus closing signal is sent to disconnect the common bus from the channel control device.

4 is a block diagram of the pseudo-input / output control device shown in FIG. 3, in which 10 is an interrupt control circuit, 11 is an address selection circuit, 12 is a direct memory access (DMA) control circuit, 13 is a timer, 14 is a control register, and 15 is a A databus multiplexer driver, 16 is a command decoder, 17 is a parity check circuit (PC), 18 is a parity generator (PG), 19 is a databus receiver and 20 is an address bus driver.

When address signals and control signals (write or read instructions) of the pseudo-input and output devices are sent out from the central control device via the gp, jp signal lines, they are detected by the address selection circuit 11.

(I) Operation in the program control mode will be described below.

(1) Writing to Control Register 14 (Program Control Mode)

In the address selection circuit 11, the write setting signal of the control register 14 to the control register 14 designated by the address is matched with either the unique address assigned to the pseudo-input / output control device or the address set in the IOAR 149. SET) and the register selector circuit REG SEL are sent, and any of the various registers 140 to 149 in the control register 14 is selected.

On the other hand, data information (including parity bits) is sent to the data bus receiver 19 via the fp signal line, and the information is written into the register selected from the control register 14 via the parity check circuit 17.

Reference numeral 140 denotes a device status register (DSR), which designates timeout information, data error information, and completion information.

141 is a byte counter register (BCR), which is a register that specifies the number of bytes of data to be transferred.

142 is a memory address register (MAR), which is a register indicating a target address of information to be transmitted.

Reference numeral 143 denotes a command register (CMR), which is a register that designates a DMA control operation such as reading to a memory or writing designation by an operation of the pseudo-input / output device itself by receiving a command from the central controller.

144 and 145 are data buffer registers (DBRO, 1), and when the read data from the channel controller is temporarily stored, the contents of the register are sent out to the data buffer when a read command is sent from the channel controller. .

146 is a mode register (MODR), which is a register specifying a normal mode or an operation mode of a byte or word.

147 is an interrupt level register (IRLR), which specifies a different interrupt level for each input / output controller.

148 is an expansion memory address register (EAR), which is a register that specifies an expansion address of the expansion memory.

149 is an I / O address register (IOAR), which is a register specifying the address of the I / O control device in order to select an address of each input / output control device.

(2) Readout of control register 14 (program control mode)

The address selection circuit sends a read setting signal (SET) and a register selection signal (REG SEL) of the control register 14, and selects an arbitrary register from various registers 140 to 149 in the control register 14. do.

In addition, a gate signal (GATE) for reading a register is sent, and a selection gate signal is sent to a register selection terminal (REG SEL) of the data bus multiplexer driver 15.

The information in the designated register in the read and designated control register 14 is taken out by the data bus multiplexer driver 15 and sent to the main memory via the fp line.

(II) Next, operation by the direct memorer access transfer mode will be described.

(1) Write to data buffer registers 144,145 by direct memory access transfer mode

The pseudo-input / output device is a device dependent on the channel control device. When the data is supplied to the control register 14 by the program control mode, the pseudo-input / output device starts the direct memory access transfer mode (independent operation) when the start bit of the command register 143 is turned on.

The information in the command register 143 translates the command information in the command dego order 16 and sends the DMA start request signal (RQDMA), the write command signal (WRITE), etc. to the DMA control circuit 12.

On the other hand, address information of the memory address register 142, that is, address information of the main memory device, is sent to the address bus driver 20 and sent to the main memory device via the gp signal line.

The DMA control circuit 12 sends a blown signal BFSET for taking the data sent from the main memory into the buffer buffers 144,145.

From the main memory, data is sent to the data bus receiver 19 via the fp line, and the data is sent to the parity check circuit 17, and then written to the dada buffer registers 144,145. Since the amount of data is set in the multiple address areas of the main memory in the direct access transfer mode operation, data is written to the data buffer registers 144,145 while updating the address of the memory address register 142 by +1.

The MA + 1 terminal of the DMA control circuit 12 sends this address update information.

The byte counter register 141 is decremented by -1 at the end of one transmission, and transfer ends when the counter value written to the byte counter register reaches zero.

The interrupt control circuit 10 receives an interrupt request signal (RQINT) to the central control unit as a signal for reporting the end of the operation, such as the completion of the DMA transfer or the timeout failure detection, and is transmitted through the ip signal line. do. The interrupt level register 147 and the input / output device address register 149 transmit the interrupt level information and the corresponding input / output device number to the terminals IAW 00 to 07 of the databus multiplexer driver 15, and the information of the device status register 140 via the fp line. To the central control unit.

The IAWOP in the interrupt control circuit 10 is a signal terminal for opening the output gate of the interrupt address word, IRL is the interrupt level setting signal terminal, and MOD is the designation terminal for the operation mode. The IOA in the address selection circuit 11 is an input terminal of the address information of the input / output device, SELECT is a selection signal terminal of the data buffer registers 144,145, and RESET is a reset terminal of the DMA control circuit 12.

In addition, the DBOP of the DMA control circuit 12 is a signal terminal for opening a sending gate of data from the data bus multiplier driver 15, and an ABOP is a signal terminal for opening a gate for sending address information of the address bus driver 20.

(2) Reading Data Buffer Registers 144,145 in the Direct Memory Access Transfer Mode

The channel controller starts the direct memory access transfer mode (independent operation) by the start bit of the command register 143 in the pseudo-input-output controller.

The information in the command register 143 translates the command information in the command decoder 16 to transmit the DMA start request signal (RQDMA), the read command (READ), and the transfer unit designation (WORD) to the DMA control circuit 12.

On the other hand, address information of the memory address register 142, that is, address information of the main memory of the transmission line, is sent to the address bus driver 20 and sent to the main memory via the gp signal line. The DMA control circuit 12 sends a signal DBOP that opens a gate for sending data.

The data in the data buffer registers 144,145 are sent to the main memory via the data bus multiplexer driver 15, and also via the fp line.

At the time of reading, the data in the data buffer registers 144, 145 is read while updating the address of the memory address register 142 by +1 as in the case of the writing described in (1). When the read transfer to the main memory is completed, the byte counter register 141 sends an interrupt request signal (RQINT) to the interrupt control circuit 10, and the interrupt control circuit 10 again sends an interrupt request signal to the central controller via the ip signal line. do.

The interrupt level register 147 and the input / output device address register 149 transmit the interrupt level information and the corresponding input / output device number to the IAW ₀ to ₀₇ terminals of the databus multiplexer driver 15, and at the same time, the information in the device status register 140 It is sent to the central control unit via.

As mentioned above, although the normal diagnostic function of the pseudo-input / output control apparatus was described, compared with the general input-output control apparatus in the pseudo-input / output control apparatus of the invention, the mode register 146, the interrupt example register 147, and the input / output device address register 149 were newly renewed. It is installed.

By setting the mode register 146 in the pseudonorma1 operation mode, it is possible to send various abnormal signals to perform the normal operation, so that it is easy to determine the detection function of the failure of the input / output control device connected to the common bus. .

FIG. 5 shows a specific circuit of the address selection circuit 11 shown in FIG. Numeral 22 denotes an input / output controller address register, and a variable register unique to this pseudo I / O controller.

This input / output control device address register 22 has a variable function, so that the unique address of each input / output device (input / output control device) can be pseudo. The address information of the input / output device is written to Gabon register 22 in advance via the fp line.

On the other hand, the address information sent via the gp signal line is compared with the input / output device address information (IOA) in the address comparison circuit 23, and if it matches, the program mode control circuit 24 is started, and the register selection circuit 26 is set.

25 indicates address information sent via the gp signal line.

The input / output device address information (IOA) is unique to each input / output device (input / output control device), but the pseudo input / output control device according to the present invention is variable.

By having a variable I / O device address as described above, a unique address of each I / O control device can be considered.

6 is a flow chart of the diagnostic method of the channel control apparatus according to the invention.

First, in step S100, the central controller detects a system failure. Subsequently, in S101, the central control unit performs an obstacle analysis, and proceeds to S102 in the case of a channel control device / input / output control device related obstacle.

In step S102, the discharge processing request of the channel control apparatus, that is, the termination process of the channel control apparatus in operation is performed. Next, in step S103, the common bus is closed. Since the closing of the common bus has not been possible in the related art, it is not possible to separate and remove the failure of any device of the channel control device or various input / output control devices.

In step S104, the channel control device CHC and the pseudo-input / output device PIO are connected. .

Subsequently, in step S105, a diagnosis of the channel control device is executed using the pseudo-input / output control device inside the channel control device.

Subsequently, in step S106, the central control apparatus sends out a diagnostic command, reads the diagnosis result and compares it with the correct information to determine GOOD / NO GOOD.

If the determination result is normal, the pseudo-input / output control device is closed in step S107 and the closing of the common bus is canceled. On the other hand, if the determination result is abnormal (NOGOOD), the flow advances to step S109 to repair the channel control device CHC. .

If the result of the determination in S106 is normal, the common bus interface of the channel control device is normal, and it is found that the cause of failure of the system is in the input / output control device and the input / output device connected to the channel control device via the common bus.

Subsequently, in step S108, the process of releasing the request for discharging the channel control device CHC, that is, enabling the operation of the input / output control device connected to the channel control device is performed. Next, as a next step, various input / output control devices that are actually connected from the channel control device via the common bus are designated, and diagnosis corresponding to the configuration is sequentially performed.

As described above, the present invention provides a pseudo I / O control device and an I / O device that can simulate the operation of the I / O control device in the channel control device. Since the pseudo I / O control device is integrated circuit, the channel control device is enlarged. In addition, when the pseudo-input / output control device is set on the common bus, the limitation of the length of the common bus and the separation problem of the common bus may occur. However, when the pseudo I / O control device is mounted in the channel control device as in the present invention, the common bus can be easily separated. .

In addition, since the normal operation can be performed, it is advantageous to easily diagnose the detector concentration of the failure of any input / output control device connected to the common bus.

Furthermore, since the diagnosis is performed by operating the pseudo I / O control device, it is possible to fix the diagnostic test data, so that it is easy even when various I / O control devices are connected to the common bus, and the channel control device can be diagnosed at high speed. have.

Claims (11)

By command from the central control unit (1), a predetermined common bus Inter Face the input-output control unit (4 ₀ ~4 _0n) input-output device (5 ₀ ~5 _0n) via the connection to the common bus by the control flow control In the channel control apparatus 3, common to a plurality of input / output control apparatuses 4 ₀ to 4 _0n connected to the respective channel control apparatuses 3 ₀ to _{3 3} via a common bus, and a plurality of channels. A common pseudo-input / output control device 9 is also provided in the control device ₃ in correspondence with the respective channel control devices 3 ₀ to _{3 3} , and the common bus is separated or connected with the command of the central control device 1. An automatic diagnosis method for a channel control device, characterized in that the automatic diagnosis of the channel control device (3) is performed. A channel control device (3) for controlling an input / output device via an input / output control device connected to a common bus by a common bus interface control procedure predetermined by a command from the central control device (1), wherein each channel control device Pseudoimmune input / output control devices common to a plurality of im-output control devices 4 ₀ to 4 ₃ connected via a common bus (3 ₀ to _{3 3} ), and also common to the plurality of channel control devices 3 ( And 9) corresponding to each channel control device. 3. The channel control apparatus according to claim 2, wherein an automatic cutting / connection means for automatically cutting / connecting the common bus is provided at the command of the central control apparatus. 2. An automatic diagnosis method for a channel control apparatus according to claim 1, wherein an automatic cutting / connection means for automatically cutting / connecting said pseudo-input / output control apparatus (9) is provided at the command of said central control apparatus (1). 2. A method for diagnosing a channel control device according to claim 1, wherein said pseudo input / output control device (9) makes it possible to programmatically set the addresses of the input / output control devices (4 ₀ to 4 ₃ ) to arbitrary addresses. 2. The automatic diagnostic method of a channel control apparatus according to claim 1, wherein said pseudo-input and output control apparatus (9) makes it possible to programmatically set the interrupt level to the central control apparatus (1). 2. The automatic diagnostic method of a channel control apparatus according to claim 1, wherein said pseudo-input and output control apparatus (9) enables the transmission of parity-era data and the timeout operation of the common bus exclusively by a program instruction. 3. A channel control apparatus according to claim 2, wherein an automatic cutting / connection means for automatically cutting / connecting said pseudo-input / output control apparatus (9) is provided at the command of said central control apparatus (1). _3. A channel control apparatus according to claim 2, wherein said pseudo input / output control device (9) makes it possible to programmatically set an address of an input / output control device (4 ₀ to 4 ₃ ) at an arbitrary address. · 3. A channel control apparatus according to claim 2, wherein said pseudo-input / output control unit (9) makes it possible to programmatically set the interrupt level to the central control unit (1). 3. The channel control apparatus according to claim 2, wherein the pseudo-input and output control apparatus (9) enables parity-era data transmission and time-out operation exclusive to the common bus by a program instruction.

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