JPS6218067B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for diagnosing a bidirectional bus of a data processing device.

Conventionally, in information processing devices having this type of bidirectional bus, bus diagnostic tests have been performed by executing bus transfers between devices. In this type of bus diagnosis method, if a failure occurs in the bus interface circuit of either the bidirectional bus itself or the device that performs bus transfer and bus transfer is not performed normally, the fault location can be found through diagnosis. The disadvantage was that it was difficult to In addition, when testing a device connected to this type of bidirectional bus, there is a drawback that a test device such as a bus simulator or the like is required for the device to be transferred to the bus or to act in place of the device.

The object of the invention is to enable a device connected to a bidirectional bus to initiate bus transfers, output data, its own device address, and control signals on the bus;
When the device address on the bus matches the device address of that device, the control signal inputs data on that bus or outputs data onto that bus, thereby performing a signal loopback test of the bidirectional bus. By diagnosing the bus interface circuit in the bus and its equipment,
It is an object of the present invention to provide a diagnostic method that solves the above-mentioned drawbacks, makes it easy to isolate the location of a failure, and makes it possible to test bidirectional buses and bus interface circuits using the device alone.

According to this invention, when a device connected to a bidirectional bus has a circuit that outputs data, a device address, and a control signal to the bus, and the device address of the bus matches the device address assigned to the device, , a circuit that inputs data on the bus or outputs data to the bus according to a control signal of the bus, and the device outputs data, its own device address, and a control signal to the bus,
The device inputs data from the bus according to the control signal of the bus because the device address of the bus matches the device address of the device, or the device inputs its own device address and control signal to the bus. When the device address of the bus matches the device address of the device, the device outputs data to the bus according to the control signal of the bus, and at the same time inputs data from the bus to output data. The input data is verified, and the device itself diagnoses the operation and data path of the bus interface including the bidirectional bus and the circuits of the device.

Next, embodiments of the invention will be described with reference to the drawings. The figure is a block diagram of a bidirectional bus interface portion of a device showing one embodiment of the present invention, and the configuration will be explained below.

The bidirectional bus AO consists of a data bus A1, an address bus A2 that transfers the device address of the destination device, and a bus control line A3 that controls writing data to and reading data from the destination device. configured. Data bus A1 is connected to data input register C5 via receiver C1, and the output of data output register C6 is connected to data bus A1 via three-state driver C3. Address bus A2 is connected to address comparison circuit C8 via receiver C2, and the output of address output register C7 is connected to address bus A2 via three-state driver C4. Address comparison circuit C8 outputs address match signal B
2 is output to the input/output control circuit C9.

A bus control line A3 common to each device connected to the bidirectional bus A0 is connected to an input/output control circuit C9,
The input/output control circuit C9 controls the input strobe of the data input register C5 and the three-state driver C3.
and a signal for controlling the output enable terminal of C4. The bus interface control circuit C10 is a bidirectional bus A0.
This is the main control circuit that controls the input/output operations of the bus interface part of this device connected to the device, and inputs data from the data input register C5 via the data input line B4, and inputs data from the data input register C6 and the address output register. The data to be transferred to the partner device and the device address for selecting the partner device are sent to C7 through the data output line B5 and the address output line B, respectively.
6, and exchanges an input/output operation control signal B3 with the input/output control circuit C9. The diagnosis notification line A4 is connected to the bus interface control circuit C10 of each device connected to the bidirectional bus A0, and transmits a signal notifying that the device is in a diagnostic mode and a signal indicating the diagnosis result of each device. .

Next, the operation of the embodiment shown in this figure will be explained in detail. Although the details of the transfer method of the bidirectional bus A0 will be omitted, the transfer operation between each device is roughly performed as follows. When a device connected to bidirectional bus A0 performs data transfer with another connected device, the former device issues a bus occupancy request. Bus occupancy requests from each device are prioritized.
If multiple bus occupancy requests occur at the same time, devices with lower priority levels will not be allowed to occupy the bus. Therefore, only one device can occupy the bus at any given time, and the device that has acquired the right to occupy the bus will hereinafter be referred to as the master device.

The master device initiates bus transfer and transfers address bus A.
2, specify the destination device by outputting the device address of the destination device. The designated device is hereinafter referred to as a slave device. The master device notifies the slave device whether the transfer is a data write transfer or a data read transfer using the bus control line A3, and releases the bus occupation when the data transfer is completed. Both the master device and slave device have the same bus interface hardware structure, and a device connected to bidirectional bus A0 can be either a master device or a slave device.

When the master device performs a data write transfer to the slave device, the bus interface control circuit C10 of the master device uses the data output register C6.
and the device address of the slave device in the address register C7, and cause the input/output control circuit C9 to output a signal to the bus control line A3 to notify that it is a data write transfer using the input/output operation control signal B3. At the same time, input/output control signal B
1 to enable the outputs of three-state drivers C3 and C4, output the contents of data output register C6 and address output register C7 to data bus A1 and address bus A2, respectively, and write data to the specified slave device. After the input, the bidirectional bus A0 is released.

On the slave device side, an address comparison circuit C8 compares the device address on the address bus A2 with the device address assigned to the slave device itself, and if they match, outputs an address match signal B2 to the input/output control circuit C9. When the input/output control circuit C9 learns from the bus control line A3 that it is a data write transfer from the master device, it outputs the input/output control signal B1.
After inputting the data on the data bus A1 to the data input register C5, the input/output operation control signal B3 notifies the bus interface control circuit C10 that the data has been input.

When the master device performs a data read transfer to the slave device, the bus interface control circuit C10 of the master device uses the address output register C10.
The device address of the slave device is set in 7, and the input/output control circuit C9 is set using the input/output operation control signal B3.
The three-state driver C outputs a signal notifying data read transfer to the bus control line A3, and at the same time outputs the input/output control signal B1.
After specifying the slave device by enabling the output of 4 and outputting the contents of the address output register C7 to the address bus, the data output from the slave device to the data bus A1 is transferred to the data input register C5 by the input/output control signal B1. When the input signal is input to the bidirectional bus A0, the bidirectional bus A0 is released.

On the slave device side, the device addresses are compared by the address comparison circuit C8 as in the case of data write transfer, and if they match, an address match signal B2 is output to the input/output control circuit C9. Input/output control circuit C
9 is a bus interface control circuit C1 based on an input/output operation control signal B3 when it learns that data is to be read and transferred from the master device via the bus control line A3.
Notify 0. Bus interface control circuit C1
0 sets data in the data output register C6, the input/output control circuit C9 enables the output of the three-state driver C3 by the input/output control signal B1, and outputs the contents of the data output register C6 to the data bus A1.

The data return transfer operation of the bidirectional bus during diagnosis is performed as follows. When a diagnostic start instruction is transmitted to the bus interface control circuit C10 of each device through the diagnostic notification line A4, the bus diagnostic test is sequentially started from the device that has become the master device.

Diagnosis of data write transfer operation is performed as follows. The bus interface control circuit C10 of the master device that performs the diagnostic test sends the test write data to the data output register C6 and the device address of the master device itself to the address output register C7.
and instructs the input/output control circuit C9 to write and transfer data to the slave device using the input/output operation control signal B3. The input/output control circuit C9 controls the three-state driver C by the input/output control signal B1.
Enable the outputs of registers C6 and C4 to data bus A1 and address bus A2.
It outputs the contents of C7 and outputs a signal notifying data write transfer to bus control line A3.
Since the device address on the address bus A2 is the device address of the master device itself, the address comparison circuit C8 of the master device outputs the address match signal B2, and as in the case of inter-device transfer described above, the master device itself becomes the slave device. These operations will be performed at the same time. That is, the input/output control circuit C9 of the master device receives a signal on the bus control line A3 from the master device notifying that there is a data write transfer, and as a slave device, generates the input/output control signal B3 to transfer the data on the data bus A1. The data is input to the data input register C5, and the input/output operation control signal B3 notifies that the data has been input to the bus interface control circuit C10 as a slave device.
The bus interface control circuit C10 inputs data from the data input register C5 and performs diagnosis by comparing this with the test write data.

Diagnosis of data read transfer is performed as follows. The bus interface control circuit C10 of the master device that performs the diagnostic test sets the device address of its own device in the address output register C7, and then uses the input/output operation control signal B3 to read and transfer data from the slave device to the input/output control circuit C9. instruct. The input/output control circuit C9 enables the output of the three-state driver C3 using the input/output control signal B1, outputs the contents of the address output register C7 to the data bus A2, and also controls the bus by sending a signal notifying data read transfer. Output to line A3. Similar to the data write transfer diagnostic operation described above, the address comparison circuit C8 of the master device outputs the address match signal B2, and the master device itself simultaneously operates as a slave device. The input/output control circuit C9 receives a signal notifying data read from the master device on the bus control line A3, and notifies the bus interface control circuit C10 as a slave device using the input/output operation control signal B3. When the bus interface control circuit C10 as a slave device sets test read data to the data output register C6, the input/output control circuit C9 enables the output of the three-state driver C3 from the input/output control signal B1, and the contents of the data output register C6. is output to data bus A1. As a master device, the input/output control circuit C9 uses the data bus A by input/output control signal B1.
After setting the data on data input register C5, the bus is released. As a master device, the bus interface control circuit C10 reads data from the data input register C5 and performs diagnosis by comparing it with the test input data.

When the bus interface control circuit C10 finishes diagnosing the data write transfer operation and the data read transfer operation, it outputs the diagnosis result to the diagnosis notification line A4. Through the above operations, each bus signal of the bidirectional bus A0 is looped back as shown by the dotted line in the figure.
The bus and the bus interface portion of the device are diagnostically tested by the device itself.

As explained above, the bidirectional bus diagnostic method of the present invention is such that each device connected to the bidirectional bus independently performs a data loop test on the bidirectional bus, thereby detecting the bidirectional bus and the bus interface. This has the effect of making it easier to diagnose the failure of the Ace circuit.

[Brief explanation of the drawing]

The figure is a block diagram showing a bus interface portion (the portion surrounded by a dashed line in the figure) connected to a bidirectional bus of a device showing an embodiment of the present invention. A0: bidirectional data bus, A1: data bus, A2: address bus, A3: bus control line, A
4: Diagnosis notification line, B1: Input/output control signal, B2:
Address match signal, B3: input/output operation control signal,
B4: Data input line, B5: Data output line, B
6: Address output line, C1, C2: Receiver, C
3, C4: Three-state driver, C5: Data input register, C6: Data output register, C
7: address output register, C8: address comparison circuit, C9: input/output control circuit, C10: bus interface control circuit.

Claims (1)

[Claims] 1. In a data processing device having a bidirectional bus, a circuit that outputs data, a device address, and a control signal to a device connected to the bus, and a device address of the bus and a device assigned to the device. The circuit includes a circuit that inputs data on the bus or outputs data to the bus using a control signal of the bus when the addresses match, and a diagnosis notification line, and the diagnosis notification line instructs each device to start diagnosis. Then, the device outputs data, its own device address, and a control signal to the bus, and the device outputs the data, its own device address, and a control signal to the bus, and the device is activated by the control signal of the bus because the device address of the bus matches the device address of the device. input data from the bus;
In addition, the device outputs its own device address and control signal to the bus, and when the device address of the bus matches the device address, the device outputs data to the bus using the control signal of the bus. At the same time, by inputting data from the bus, output data and input data are collated, and the device itself diagnoses the operation of the bus interface including the bidirectional bus and the circuit of the device, and the data path. A bidirectional bus diagnostic method characterized by: