SU1305823A1 - Digital frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering and provides a reduction in the level of spurious spectral components in the output signal. The digital synthesizer contains registers of 1.5 frequency codes, pulse generator 2, accumulating adder (NS) 3, subtraction unit of 4 codes, trigger 6, comparators 7, 11, 12, 13 codes, switch 8, adders 9, 14, 15, 16 codes, the decoder 10, the DAC 17, the lowpass filter 18. Register 1 contains the code of the number n, and register 5 contains the code of the number N, which determines the capacity of the NS 3. In NA 3, the code of the number n is summed with the code of the number obtained in the previous clock cycle. The subtraction unit 4 determines the difference between the current code value in HC 3 and the register code 5. Comparator 7 generates a signal to write the code of subtraction unit 4 in the HC 3 if the current value of the HC code 3 exceeds the value of the code N. The code sequence at the output of the HC 3 is a sequence of phase codes. The HC 3 code change interval, equal to N, is divided into four subintervals. Using comparators 11–13, a subinterval is defined, in which the current value of the NS 3 code is located. The decoder 10 generates control signals to the adder 9 depending on which subinterval is in the current NA 3 code value. In the adder 14, the addition of the approximating function occurs (with NA 3) and the correction function (with adder 9). 1 il. I (L p1 eo SD: o

Description

The invention relates to radio engineering and can be used in radio transmitting and receiving devices.

The aim of the invention is to reduce the level of spurious spectral components in the output signal.

The drawing shows an electrical structural diagram of a digital frequency synthesizer.

The digital frequency synthesizer contains the first register of the 1 frequency code, the generator of 2 pulses, accumulating adder (NS) 3, block 4 of the code subtraction, the second register 5 of the frequency code, trigger 6, the first comparator 7 codes, switch 8, the first adder 9 codes, the decoder 10, the second comparator 11 codes, the third comparator 12 codes, the fourth comparator 13 codes, the second adder 14 codes, the third adder 15 codes, the fourth adder 16 codes, digital-to-analog converter (D / A) 17 and the low-pass filter 18.

The synthesizer works as follows.

In the initial state, the code of the number n is written into the first register 1, and the code of the number N defining the capacitance NS 3 is written into the second register 5. At each operation cycle in HC 3, the code of the number n is summed up by a synchronizing pulse from the generator 2 output. with the code number. Obtained in the previous cycle of operation, In NS 3, a sequence of codes is formed) P p (p 1, 2, 3, .... is the number of the cycle of operation of the digital frequency synthesizer). At the same time, in each clock cycle in the subtraction unit, the difference between the current code value in HC 3 (code K ns (p)) and: the code value in the second register-5 Kjg (p)

 K «s (p - N.

In the first comparator 7, the current code HC 3 is compared with the code of the second register 5, and a write signal is generated at the output of the first comparator 7 if the current value of K., exceeds the value of code N. This signal triggers the trigger signal. ,

in HC 3 is carried out with standard

IK.

The sequence of codes at the output of the HC 3 can be considered as the sequence of phase codes in the interval Cf € (0 „.,. M). The conversion of the indicated codes into amplitude codes of the output oscillation is carried out in the remaining elements of the digital frequency synthesizer.

The specified transformation function is represented as a sum

fO

f5

20

9g. -1 F c ,,, (PL + L.KHC (PIJ L ns (.p) J

 . g P. ns (p) FKE Hcipi,

where, 1 - approximating

25

(p).

 Hc (pl

j function

S is the number of argument split subintervals; J - corrective

function; (- switching

function

As an approximating function, p {Kc, pL, the direct or inverse function value is used, and the correction function is formed by the shift and summation operations. The code change interval Kj, j, / p-jj equal to N, is divided into four

35

podintervala and with the second.

the third and fourth comparators 11-13, the definition of a subinterval, in which the current code value is found (p NA 3. For these

 The target value Kc (.; p is fed to the goals of the comparators 11-13, and codes defining the boundaries of the selected subintervals are fed to the other inputs. The outputs of the second register 5 are shifted by one second to the second group of inputs of the second comparator 11 d in the direction of the younger bits, which is equivalent to the filing of the code N / 2. To the second group

The 5 inputs of the third comparator 12 are connected to the outputs of the second register 5 with a shift by two bits towards the lower bits, which is equivalent to the filing of the code N / 4. On the second group

6 and the output of the inputs of the fourth comparator 13 of the sub code of the subtraction unit 4 to the HC 3. The outputs of the fourth adder 16 are fed. As a result, the code 3 NM is formed. This code forms a sequence of codes with in the fourth adder 16 by

TO,

in HC 3 is carried out with standard

IK.

The sequence of codes at the output of the NC 3 can be considered as a sequence of phase codes on the interval Cf € (0 „.,. M). The conversion of the indicated codes into amplitude codes of the output oscillation is carried out in the remaining elements of the digital frequency synthesizer.

The specified transformation function is represented as a sum

five

0

9g. -1 F c ,,, (PL + L.KHC (PIJ L ns (.p) J

 . g P. ns (p) FKE Hcipi,

where, 1 - approximating

five

(p).

 Hc (pl

j function

S is the number of argument split subintervals; J - corrective

function; (- switching

function

As an approximating function, p {Kc, pL, the direct or inverse function value is used, and the correction function is formed by the shift and summation operations. The code change interval Kj, j, / p-jj equal to N, is divided into four

five

podintervala and with the second.

the third and fourth comparators 11-13, the definition of a subinterval, in which the current code value is found (p NA 3. For these

 The target value Kc (.; p is fed to the goals of the comparators 11-13, and codes defining the boundaries of the selected subintervals are fed to the other inputs. The outputs of the second register 5 are shifted by one second to the second group of inputs of the second comparator 11 d in the direction of the younger bits, which is equivalent to the filing of the code N / 2. To the second group

The 5 inputs of the third comparator 12 are connected to the outputs of the second register 5 with a shift by two bits towards the lower bits, which is equivalent to the filing of the code N / 4. On the second group

3

add codes N / 2 and N / 4 or by subtracting code N / 4 from code N. The specified input codes of the fourth adder 16 are formed by shifting the bit bus. In the decoder 10, the output signals of the second, third, and fourth comparators 11-13 are decoded, and various control signals are generated depending on which subinterval the current code value is in

IS (p) Addition of the approximating and correcting functions occurs in the second adder 14, and the formation of the correcting functions in the first adder 9.

If the current value of the Ksch ./- code is in the first subinterval, T.K (. (P) N / 4, control outputs are generated at the outputs of the decoder 10, under the action of which the first adder 9 switches to the translation of the input code, t on its output a code is formed The outputs of the first adder 9 are connected to the inputs of the second adder 14 with a shift of one bit towards the lower bits, which is equivalent to a two-fold decrease in the numerical value of the input code Under the action of the signal from the decoder 10 in the second adder 14 is carried out subtracting from the code

code -t.

If the current code value (p) is in the second subinterval, i.e. N / 4 Sr Hz (,, N / 2, then the switch 8 is given a signal, under the influence of which the outputs of the second register 5 are connected to the inputs of the first adder 9 with a shift by one bit towards the lower bits. This is equivalent to the code N / 2.B the first adder 9 from the N / 2 code subtracts the current value of the Kcr-rch code, i.e. Kj -, (p) N / 2 - and in the second adder 14, the reduced value of the output code of the first adder 9 is subtracted from the code i.e.

;etc) ()

N

(p) / 2

 U5 K,

NS (p)

- N / 4.

If the current value of the code K ,,,, is in the third subinterval, i.e. N / 2, 3 N / 4, then in the first adder 9 the code N / 2 is subtracted from code K, which comes from the output of switch B.

The output code K2 -, (p, halved in the second adder 14, is added with the code K, h, i.e. the code is generated

ns (p1

i

(TO

NA

-} (9 2 Ь5 К, .р - N / 4.

If the current code value is in the fourth channel interval, i.e. 3 N / 4 ns (p) - N, then the input of the first adder 9 through the switch 8 receives without offset the code of the number N from which the code K | is subtracted (.h. The output code of the first adder 9 reduced twice the second adder 14 with the code K, (., p. i.e.

KG (P) 1/2 N + k „c, p) 1.

Formed in the second adder 14 codes podTotts to the input of the third

adder 15, the mode control of which is triggered by trigger 6. In the first half-period of the output oscillation, tertiary adder 15 operates in the broadcast mode of the input signal, and in the second half-period, in the third adder 15, the output code of the second adder 14 is subtracted from the formation of the second half period of the output

the oscillation is performed by inverting the codes on the base of N and thereby eliminating the code conversion error.

The amplitude codes formed at the output of the third adder 15 are transformed into DAN 17, and the first harmonic of the output signal is emitted in filter 18.

50

In the proposed digital frequency synthesizer, the level of the parasitic spectral components in the output signal is significantly reduced. This is due to the elimination of the conversion error of the codes when inverting the output NC 3 codes, as well as the more accurate formation of the output harmonic function.

Claims (1)

DETAILED DESCRIPTION OF THE INVENTION A digital frequency synthesizer comprising a first frequency code register, serially connected a second frequency code register, a code subtractor, an accumulator, and a first code comparator, a serially connected digital-analog converter and a low-pass filter, as well as a pulse generator, whose output is connected the synchronization input of the accumulating adder, the second input of the first code comparator is connected to the output of the second frequency code register, the second code input, the setting input and The output of the accumulating adder is connected respectively to the code of the first frequency code register, the output of the first code comparator and the second input of the code subtraction unit, characterized in that, in order to reduce the level of spurious spectral components in the output signal between the output of the second frequency code register and the input the house of the digital-to-analog converter is a serially connected second code comparator, a decoder, a switch, a first code adder, a second code adder and a third code adder, and also tr igger Compiled by Yu. Kovalev Editor O. Yurkovetska Tehred A. Kravchuk Proofreader A. Zimokosov 1463/53 Circulation 902 Subscription VNIIPI USSR State Committee. for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 . Production and printing company, Uzhgorod, ulo Proektna, 4 the third code comparator and the fourth fourth code adder and the fourth code comparator, whose output is connected to the second input of the decoder, the third input, the second and third outputs of which are connected to the third output of the third code comparator, the control input of the first code adder and the control input of the second adder, respectively CODES), the second input of which is combined with the second input of the first code adder, the second input of the second code comparator, the first input of the third code comparator and the second input The third code comparator is connected to the output of the accumulating adder, the second input of the third code comparator is combined with the Switch's code input, the second input of the third code adder, the first and second inputs of the fourth code adder, and the trigger input and output are connected to the output of the first code comparator and the control input of the third code adder, and the output of the pulse generator is connected to the synchronization input of the digital-to-analog pre-. educator