SU1305776A1 - Storage with sequential writing and reading - Google Patents

Abstract

The invention relates to computing technology and can be used in the construction of specialized devices for the orderly storage and release of information on an indiscriminate principle. The purpose of the invention is to increase the speed of the device. The device contains counter 1, elements AND 2-4, elements OR 5 and 6, shift register 7, multiplexer 8 and element 11. The register 7 consists of memory slots 10. A recirculation loop is automatically installed in the device when the information is entered, which includes only the filled memory cells 10, which shortens the memory retrieval time and enables the regeneration of the read information. 1 il. (L with about cd to 05

Description

The invention relates to computing and can be used in the construction of specialized devices for the orderly storage and release of information on an indiscriminate principle.

The purpose of the invention is improving the speed of the device.

The drawing shows a block diagram of a memory device with sequential write and read.

The storage device contains counter 1, first 2, second 3 and third 4 elements AND, the first 5 and second 6 elements OR, shift register 7, multiplexer 8 having control input 9. Register 7 consists of memory slots 10. The device also contains a fourth element And 11 and has a read input 12, a sync input 13, a write input 14, information input 15 and information output 16.

The storage device has three modes of operation: storage, recording and reading information.

In the storage mode, a logical O on the inputs 12 and 14 of the device prohibits the passage of signals through the elements AND -2-4 and It. In this case, the recorded information is stored in the storage cells 10 of the register 7.

In the recording mode, information on the device input 14 is set to logical 1, which corresponds to the resolution of signals passing through AND 2 and 4 elements. Information from input 15 through AND 2 element and OR 5 element enters input of register 7. Clock signal from input 13 through AND element 4 and the element OR 6 is fed to the input of the register 7 and information is recorded in the first cell 10, as well as a shift of the previously recorded information to the right by one cell 10. In this case, the clock signal from the output of the AND 4 element enters the input of the counter 1 and increases it the contents and the unit. The state of counter 1 indicates the number of cells 10 filled with information. The multiplexer 8, in accordance with the contents of the counter 1, connects the output of the first filled cell 10 to the input of the element 11. Next, the process is repeated in the indicated order.

In reading mode information, logical 1 is set at the input

12 devices, which corresponds to the resolution of the passage of signals through the elements And 3 and 11. The clock signal from the input 13 of the device through the element

And 3 and the element OR 6 is fed to the input of the register 7, x; moving the information to the right. At the same time, the contents of the first filled cell 10 of the register 7 through multiplexer 8, the element 11 and the element OR 5 are fed to the input of the first cell 10, forming a recirculation loop comprising only those cells 10 of the register 7 in which information was recorded. From the output of the element 11

Readable information is also fed to the information output 16 of the device.

Claims (1)

Invention Formula A sequential write and read memory device containing a shift register, a counter, AND elements and OR elements, the first input of the first element. And an information input of the device; the first inputs of the second and third AND elements are combined and are the sync input of the device, the second inputs of the first and third elements And are combined and are the recording input of the device, the second input of the second element And and the first input of the fourth element And are combined and input the reading of the device, the output of the fourth The AND element is the information output of the device and is connected to the first input of the first OR element. the second input and output of which are connected respectively to the output of the first element AND and the information input of the shift register, the synchronization input of which is connected to the output of the second element OR, the first input of which is connected to the output of the second element AND, the second input of the second element S1I and the counter input of the counter are connected with the output of the third element, And, with the fact that, in order to increase the speed of the device, a multiplexer has been introduced into it, the information inputs of which are connected to the outputs of the shift register, which controls d soe- union of the multiplexer to the outputs of the counter bit rows, and a multiplexer output connected to the second input of the fourth element I.