SU1304169A1 - Digital matched filter - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to increase the accuracy of filtering by increasing the base of pseudo-random sequences. The device contains a shift register 1, an adder 2, an additional adder 3, NOT 4 and 5 el-s, And 6 and 7 el-blocks, a digital comparator 8, a reversing counter 9, subtraction blocks 10 and 11, and AND blocks 12 and 13, block of EL or 14. 14. Il. 00 about n {about: with

Description

can be used in digital information processing systems.

The purpose of the invention is to improve the accuracy of filtering by increasing the base of 5 pseudo-random sequences.

The drawing shows a structural electrical circuit of the proposed digital matched filter.

correlation function, the number of characters of one type is usually equal to M

N-1 -2 Accordingly, the number

.K-1

signals of another type is equal to 2 + 1. You can always choose a signal whose M number is smaller in sequence than that of another. In this way.

The digital matched filter with 0 number of taps from shift register 1 holds shift register 1, adder 2 is equal to M, which is two times less

length N of a pseudo-random sequence. When passing through, -, .. - gist 1 shift of interfering signal

comparator 8, reversible counter 9, the sum in adder 2 varies between the first and second blocks 10 and 11 and is calculated in the interval from

O to M. In this case, the sum in the reverse counter 9 is also random and distributed in the interval from O to N. The 20 m code of adder 2 enters the additional adder 3 as a 4t code, for which the output of the K-th bit of adder 2 is connected to the input K + 2 bit yes additional adder 3,

additional adder 3, the first and second elements are NOT 4 and 5, the first and second elements are And 6 and 7, are digital

tannin, first and second blocks of elements AND 12 and 13, block of elements OR 14. The digital matched filter works in the following way.

The input process is a pseudo-random sequence of binary signals O arrives at the input of the shift register 1, the contents of which is advanced by clock synchronization pulses. The up / down counter 9 counts the number of single signals of register 1 bits, the shift from the first

i.e., the multiplication on the chip is realized by shifting the bonds by two bits. In the additional adder 3, the 4t code is summed with the signal N - 2M, which is fed to the first input sum. E., Multiplication by the chip is realized by shifting the links by two bits. In the additional adder 3, the 4t code is summed with the signal N - 2M, which arrives at the first input of the sum35

subtraction. Compressed signal produced by law

(4m + N-2M) C2n-4m) - (N-2M), (1)

on the last but one inclusive. Capacity 30 of torus 3. The output compressed signal of the shift register is N + 1, where N is bathed with blocks 10 and 11, the number of binary signals in a pseudo-random sequence. The amount in the reversible counter 9 is increased by one, if the input register

1 shift arrives 1, and in the last. by viitani from the doubled scientific research institute, the bit is O, and is reduced by one com-code 2 of the reversible counter 9 code in the opposite case. In the additional adder 3. The doubling of the total cases in the reversible code of the reversible counter 9 of the production counter does not change. The first and BTO ;;; 40 is driven by shifting its outputs from the input elements HE 4 and 5 and the elements AND blocks 10 and 11 of the subtraction. When naps 6 and 7 exclude, the reverse accumulation in the reversible counter 9 fails, the counter 9 fails due to the possible arrival of summatb 2 and the additional sum of single signals on both its matrix 3 interfering signals of the input signal. Adder 2 performs the sum- 45 S is distributed from -N to the signaling in the register- + bits, since the code on the E1 exit of the 1 additional shift, whose numbers with the counter adder 3 with equal probability from the end coincide with one value can be as great as

and less code on the output; odes of the reversible 50 counter 9. The subtraction unit ensures the correct calculation if the code at the summation input is greater than the code at the subtraction input. Block 10 of the subtraction provides a fuzzy computational-other, and in the extreme case, their collection, if the code 2n is greater than the code 4yu + honest can be equal. In M-after- + N-2M, and block 11 subtraction, in the case when the number of arguments is N, is usually equal if code 2n is less. The comparison of co-N 2 is 1, i.e., N is an odd odd at the outputs with an additional sum. In the M-sequence from the mamator 3 and the reversing counter 9

characters of the expected pseudo-random sequence. In any random or pseudo-random sequence formed by two signals (symbols), the number of signals of one type is always less than for

correlation function, the number of characters of one type is usually equal to M

N-1 -2 Accordingly, the number

.K-1

signals of another type is equal to 2 + 1. You can always choose a signal whose M number in the sequence is smaller than that of the other. In this way.

i.e., the multiplication on the chip is realized by shifting the bonds by two bits. In the additional adder 3, the 4t code is summed with the signal N - 2M, which is fed to the first input of the adder 3. The output compressed signal is generated using blocks 10 and 11

35

subtraction. Compressed signal produced by law

(4m + N-2M) C2n-4m) - (N-2M), (1)

30 torus 3. The output compressed signal is generated using blocks 10 and 11

 ..e. by viiitani from the doubled k-ode 2 reversible counter 9 code of the additional adder 3. Doubling the code of the reversible counter 9 is performed by shifting its outputs with the inputs of blocks 10 and 11 of the subtraction. When accumulated in the reversible counter 9, summatb 2 and in the additional accumulator 3 of interfering signals, the signal 45 S is distributed in the range from -N to +, since the code on the E1pod of the additional adder 3 with equal accuracy can be more so

produced using a digital comparator 8, which in the case of a larger code 2n opens a unit 12 of the block 12 with a single signal and passes a code from the output of the subtraction unit 10 to the output through the block of elements OR 14, and in the case of a smaller code opens the unit of a unit 13 and passes to the output through the block of elements IL 14 code from the output of block 11 subtraction. Thus, the difference modulus (1) is transmitted to the output. As a sign signal of the difference (1), the signal from one of the outputs of the digital comparator 8 can be used. In subsequent cases when the sum of S is squared in subsequent devices, the sign signal is not used. If the shift register 1 contains the required signal, the units are in those bits of the shift register 1 that are associated with adder 2 and the sum in adder 2 and in the reversible counter 9 are the same and equal to M. If this value is substituted into (1), then. If the inversion of characters occurs in the useful signal, i.e. Since the signals +1 and -1 are interchanged, in the shift register 1, the signals 1 and O change respectively, and in this case only zero signals are present at the inputs of the adder 2. In this case, the sum m in adder 2 is equal to O, and the sum in reversible counter 9 is equal to N-M. If we substitute these values in (1), we get. Thus, when the signal is inverted, the sign of the compressed signal is inverted. The N-2M signal determines the biased distribution of the compressed signal as a result of the inequality of the number 2m number N. The subtraction of this signal according to (1) centers the compressed signal.

Claims (1)

Invention Formula A digital matched filter containing a shift register, the input of which is the digital matched filter input, and an adder, in that with the order 1323/56 Random polygons pr-tie, Uzhgorod, st. Project, 4 To improve filtering accuracy when increasing the base of pseudo-random sequences, an additional adder is added, the first inputs of which are a signal input with a code (N-2M), where N is the number of shift register bits, M is the number of characters of one pseudo-random sequence value, and the second the inputs are connected to the outputs of the adder, a reversible counter, a block of elements OR, whose outputs are the outputs of a digital matched filter connected in series and connected between the outputs of the additional adder the first inputs of the block of elements OR the first subtraction unit and the first block of elements AND serially connected and connected between the outputs of the reversible counter and the second inputs of the block of elements OR the second subtraction unit and the second block of elements AND, a digital comparator, the first inputs of which are connected to the combined outputs of the reversible counter c the second inputs of the first subtraction unit, the second inputs of the digital commaparator are connected to the combined outputs of the additional adder with the second inputs of the second subtraction unit, p The left and second outputs of the digital commaparator are connected to the second inputs of the first and second blocks of elements AND, respectively, connected in series and connected between the output of the first digit of the shift register and the subtraction input of the reversible counter, the first element NOT and the first element AND, the second input of which is connected to the output of the last bit Yes shift register, connected in series and connected between the output of the last bit of the shift register and the summation input of the reversible counter, the second element NOT and the second element m and whose other input is connected to the output of the first discharge shift register, wherein the adder inputs are connected to outputs of the shift register corresponding to the symbols of one value. Circulation 902 Subscription