SU1295383A2 - Device for determining completeness properties of logic functions - Google Patents

Abstract

The invention relates to computing, can be used to recognize the functional completeness of logical function systems in the design of digital devices, as well as to control and search for 00

Description

Faults in the devices by analyzing the logical properties of the boolean functions describing the timing diagrams of their operation, and is an improvement of the invention by author. No. 1170446. The aim of the invention is to increase the reliability of control of input information by additionally determining the non-monotonicity, non-linearity and non-self-dual coefficients (logical signature coefficients). The device contains RS-flip-flop 1, operational storage blocks 2 and 3, triggers 4 with a counting input, switch 5 triggers. Herniax signals, shapers 6 and 7 pulses, D-flip-flop 8, shift register 9, elements 3 O and 11, element EQUALITY 12 element And 13, element EQUALITY 14, element 15, memory register 16, binary Smart watch 17, waiting generator 18 clocks, delay element 19, RS-flip-flops 20 and 21, bus 22 logical 1, input input 23, reset input 24, outputs 25–29 of the completeness properties set information, output 30 of the work completion signal, input 31 behind

one

The invention relates to computing, can be used to recognize the functional completeness of logical function systems in the design of digital devices, as well as to monitor and troubleshoot devices by analyzing the logical properties of Boolean functions describing their timing diagrams, and is an improvement on the known device auth. W 1170446

The aim of the invention is to increase the reliability of control of the input information by additionally determining the non-monotonicity, nonlinearity and non-self-dual coefficients (logical signature coefficients).

The drawing shows a diagram of the device.

The device contains a RS-flip-flop 1, operational storage units 2 and 3

start, element 32 hell (1rzhki, eiemesh Sh1I 33, elements AND 34 - 39, element OR 40, elements And 41 and 42, switches 43 - 45 kaialop, element 46 delay, binary counters 47 and 48, information input 49, input 50 synchronization, output 51 of information about the rank, the element OR 52, binary counters 53 and 54, accumulating adder 55, output 56 of information on the coefficient of non-self-duality, output 57 of information on the non-monotonic coefficient and output 58 of information on the nonlinearity coefficient. The proposed device distinguishes binary sequences with the same rank but otli from each other the number of pairs of neighboring sets of the corresponding Boolean functions on which the monotonicity property does not hold (by the coefficient of non-monotonicity) and the linearity property (by the nonlinearity coefficient), as well as by the number of pairs of opposite sets on which the self-dualism property does not hold (by the coefficient of non-dualism) .1 il.

triggers 4 with a counting input, switch 5 trigger signals, shapers 6 and 7 pulses, D-flip-flop 8, shift register 9, elements 10 and 11, EQUALITY 12, element E 13, element EQUALITY 14, element E 15, register 16 memory, binary counter 17, 18 clock generator, delay element 19, RS flip-flops 20 and 21, bus 22 logical 1, input input 23, reset input 24, completeness property information outputs 25-29, termination signal output 30 work, launch input 31, delay element 32, element OR 33, elements AND 34 - 39, element OR 40 ,. And 41 and 42 elements, switches 43 - 45 channels, delay element 46, binary counters 47 and 48, information input 49, synchronization input 50, output of information about the rank, OR element 52 “binary counters 53 and 54, accumulating adder 55,

output 56 of information about the coefficient of non-dual property, output 57 of information on the non-monotonous ratio, and output 58 of information on the non-linear coefficient,

The device works as follows.

Before starting work on the reset input 24, a reset pulse is applied, which sets the triggers 1.4 and 8, registers 9 and 16, binary counters 17, 47, 48, 53 and 54 and accumulating adder 55 to the zero state. At the same time, the waiting generator - the 18-clock torus is set to the first state in which there are no such pulses from its output, the RS flip-flops 20 and 21 are also transferred to the first (single) states in which the clock pulses are output from the output of the And 37 to determine properties of nonconservation of constants, and from the output of elements Compendium 38 — to determine the property of non-self-identity. In addition, from - a single output of the RS flip-flop 21, a potential control signal is output to the switch 5 of the trigger signals.

The trigger switch 5 represents a combination heme. Its i-th bit implements the following logical functions at its outputs:

f, “Q; (SGF7) Y Q, (C V9.);

 Q; V); Q,,

de f; a logical function of the first output connected to the ith information input of the second group of the channel switch 45;

the logical function of the second output connected to the counting input (i + I) -ro of the counting trigger 4 .; direct (non-inverting) output of the i-ro counting trigger 4;

inverse output of the counting trigger 4; control signal from the output of the RS flip-flop 21; control signal from i-ro output of shift register 9, Since the shift register after resetting is zero, the switching signals of even triggers in 4 from its outputs are absent, therefore

1M

- (i4i) c4

Q, Q, G ".

Ф: at the inputs of the installation, zero-counting triggers 4 are unlocked, and the counting input of the i-ro counting trigger through the switch. 5 trigger signals

5 is connected to the output of the previous () -ro trigger, forming a n bit binary counter, with the information inputs of the second switch group 45 channels

  the inverse outputs of the counting triggers 4 are connected, the binary set code o appears on the information inputs of the second switch group 44, and the information inputs of the second switch group 45

channels - dialing code All 1. I

With the input 31 of the device start pulse triggered

0 RS flip-flop 1 and at its output a potential of logical 1 appears, switching the operational storage units 2 and 3 to the recording mode of information received at input 49 of the device through the opened AND 4 element to the information inputs of operational storage units 2 and 3, Thereby, the channel switch 43 is switched to a state where the clock pulses,

0 arriving at the device input 50, pass to its output and further to the work enable inputs of the operational storage units 2 and 3 and through the input delay element 46 to the n-bit of the binary counter 47, which serves as the address counter. Hell, resna information from the outputs of the binary counter 47 enters the information inputs of the first group of switches 44

0 and 45 channels, which after the start signal of the device are connected to the address inputs of both operational storage units 2 and 3. In this way, the same information scheme is recorded in 5 with the same addresses, and the first bit of the input binary sequence is recorded at the address O. All. At the same time, the number of units in the analyzed binary sequence arriving at the input 49 of the device is counted with the help of a () -binary binary counter 48, at the counting input of which it receives information the resulting output element And 42 as a result of the construction of the input information from the output element And 41 clock pulses from the output of the switch 43 channels.

five

With the input pulse input 23 input, the RS flip-flop 1 is switched to the zero state, at which the elements 41 and 42 are closed, and both operational storage units are switched to the read mode of the recorded information. This starts the waiting generator 18 cycles and the first pulse from its output through the prepared elements And 37 and 38 is fed to the inputs of the elements And 10 11 and 35, respectively. In addition, the switches 44 and 45 of the channels are switched so that the information inputs of the second group are connected to their outputs, i.e. the address inputs of block 2 are switched to counting triggers 4, the address inputs of block 3 to the corresponding outputs of switch 5 of trigger signals, and through the switch of channels 43, the outputs of the work of blocks 2 and 3 begin to receive pulses from the output of the waiting generator 18 clock cycles.

Element AND 10 is the determinant of the nonzero constant zero property. By the moment the first clock pulse arrives at one of its inputs from the output of element I 37 at its other input from the output of block 2, the value of the Boolean function on the zero set is connected, therefore, if the logic function being analyzed does not keep the constant zero, then the clock pulse passes the output of the AND 10 element and translates the first trigger of the memory register 16 to the one state, which is fixed at the output 25 of the device.

Similarly, AND1I is the determinant of the property of nonconservation of the constant one. One of its inputs is connected to the inverse output of block 3, so when the first clock pulse arrives from the output of element 37, the inverse value of the function being analyzed appears on this input. In the set All 1. If the logic function being analyzed does not save the constant one, the clock pulse passes at the output of the element I P and sets the second register trigger 16 to the one state, fixed at the output 26 of the device.

The first after entering a clock pulse, the delay element 19 is passed, translates the RS-flip-flop 20 into the second

five

0

five

The (zero) state in which the clock pulses are not allowed to pass to the output of element 37 and enters the counting input of the first trigger of the binary counter formed from the individual counting triggers 4 using the switch 5 of the trigger signals. The specified counter Starts counting the clock pulses coming from the delay element 19, while the direct outputs of the counting triggers 4 are connected to the address inputs of block 2 through the switch 44 of the channels and the inverse outputs of these triggers through the switch of the 45 channels to the address inputs of block 3.

Thus, at the outputs of the EQUALITY element 12, which is the determinant property of non-self-dualism, connected to the direct outputs of both operational storage units, at the same times of the start of the analyzed logical function are on opposite sets. If the function being analyzed is incompatible, then at least on one pair of opposite sets the values of the function are the same. At the same time, the clock pulses from the output of the AND 38 element, the leading moments of the change in the states of the flip-flops 4, by the amount determined by the delay element 19, pass to the output of the AND 35 element and set the third trigger of the memory register 16 to one state, fixed at the output 27 devices. In addition, the pulses from the output of the element 35 are sent to the counting input of the binary counter 53 in the amount corresponding to the non-self-duality coefficient, the result of which is determined at the output 56 of the device.

After going through 2 states at the output of the n-th counting trigger, a negative voltage drop appears, from which driver 7 generates a control pulse. The latter translates the RS flip-flop 21 into the second (zero) state, in which the clock pulses pass to the output of the element AND 39 connected to the elements 13 and 36. In addition, the pulse from the output of the imager 7 writes 1 to the D-trigger 8 and the first bit of the shift register 9, while at the output of the first bit of the shift register 9

0

five

0

five

20

a signal f appears, switching the first counting flip-flop 4, according to which each trigger is held in the zero state. The delayed clock pulses through the first bit of the switch 5 of the trigger 5 signals bypass the first counting trigger to the counting input of the second trigger, and to the first address input of unit 3 through the switch 45 channels have a connected inverse output of the counting trigger.

In this way, the binary counter formed from the counting triggers 4 and the bits of the switch 5 of the trigger signals continues to count the clock t of the output of the delay element 19, while the blocks 2 and 3 are alternately connected to the first inputs of the element And 13 and the element EQUITY 14 values of the analyzed logical function on all pairs gluing together on the first variable of sets. ,,

Element And 13 is the determinant of the property of non-monotony. Its second input is connected to the inverse output of block 3; therefore, at the same moment of time, at the first two inputs of the AND 13 element, the values of the analyzed function on the two gluing sets appear, and. the function of the function on the larger of them turns out to be inverted. Thus, if the logical function is non-monotonic, then the HOWs on one pair of glued together ("Abor values of the function on the smallest of them are greater than on large

35

shem

with the first two

the inputs of the element And 13 is the potential of logical 1, the clock pulses arriving at its third input from the output of the element 39, pass to the output of the element 13 and set the fourth trigger of the register 16 memory in the unit state, fixed at the output 28 of the device. In addition, pulses from the output of the element 13 are passed to the counting input of the binary counter 54 in an amount corresponding to the non-monotonicity coefficient, the result of which is determined at the output 57 of the device.

Simultaneously with the determination of the non-monotonicity property, the nonlinearity property is determined.

0

,

d

five

5 Q

The determinant of the nonlinearity property is the EQUALITY element 4, the inputs of which are connected to the direct outputs of blocks 2 and 3, and the output is connected to one of the inputs of the AND 36 element. Therefore, if the logical function is nonlinear, then at least one pair of glued along the essential variable of the sets, the function receives the same values, and the clock pulses arriving at the other input of the AND 36 element from the output of the AND 39 element pass to the output of the AND 36 element and arrive at the counting input of the counter 17. In the event that on one pair or at full speed the functions glued on the first variable sets the same values, from the output of the AND 36 element to the counting input (n-1) -disable binary counter 17 will not arrive respectively either or exactly pulses, as a result the indicated counter will be reset to zero of the element OR 33, connecting:; - by its inputs to the outputs of all bits of counter 17, the potential of logical O will be formed. After going through the states at the output of the n-th counting trigger 4, a negative voltage difference is again formed, Vatel 7 throws trigger discharge of the first shift register 9 in the null state, due to a single state of D-flip-flop 8, a second discharge recorded register i, due to a single state of the flip-flop of the first discharge shift register 9. Thus, from the output of the second bit of the shift register 9, the switching signal F of the second counting flip-flop 4, which acts similarly to the signal P ,, i.e. holds in the cool state the second trigger 4j signal to the counting input of the third trigger 4 enters the second trigger from the output of the first counting trigger, and the second address input of the block 3 through the switch 45 channels connects the inverse output of the second counting trigger 4. Pulses from the output shaper 7, having passed the RSHI element 40, does not go further to the output of the AND 34 element and does not set the fifth register trigger

16 memories per unit.

r, tt-t

In any other case, when the number of pairs of gluing sets, on which the function takes the same values, differs from the numbers O and 2 at the output of the element OR 33 forms a potential of 1, allowing the passage of a pulse from the output of the element OR 40 to the installation input of the unit The fifth trigger of the memory register 16, which is established in a single state, is fixed at the output 29 of the device and testifies to the nonlinearity of the analyzed logic function. Passing the delay element 32, the pulses from the output of the element OR 40 rewrite the contents of the counter 17 into the accumulating adder 55 and, on the trailing edge, set the initial zero state of the counter 17, preparing it to work on the next variable. From the outputs of the matrix 55, information about the nonlinearity coefficient is transmitted to the output 58 of the device.

Similarly, the device operates up to the switching of the nth counting trigger 4, while in register 9 of the shift after every () clock cycles there is a shift of logical 1 towards the higher bits and filling of the lower bits of logical 0.

After the binary counter formed from the counting triggers 4 calculates 2 states from the moment of switching the nth trigger, a negative voltage drop is generated at the output (nl) -ro of the counting trigger, which after forming with the help of the former 6 impulses passes through the prepared element Both 15 and the element OR 40 at the input of the element AND 34 and the cutter 32 of the delay element - at the census input of accumulating adder 55, at the input of the zero setting of counter 17, and also the stop input of the generator 18 cycles and stops at the same time at output 30 ow are pulse completion of the device, signals that the received logic values of the signature of the analyzed logical function and its coefficients may be read from the register 16, memory counter 48,

VIIPPI

Order 618/55

Polygon pr-tie, Uzhgorod, st. Project, 4

fO

f5

20

25

53 and 54 and accumulating adder 55.

The proposed device is characterized by higher reliability of control of digital blocks, since it additionally provides error recognition in binary sequences corresponding to the degree of change in the logistic properties of non-monotonicity, nonlinearity and non-dualism, i.e. distinguishes binary sequences with the same rank, but differing from each other in the number of pairs of adjacent sets of the corresponding Boolean functions on which the monotony property does not hold (non-monotonicity coefficient) and the linearity property (nonlinearity coefficient), as well as in the number of pairs of opposite sets on which the property of self-dualism is fulfilled (by a coefficient of non-self-dualism).

Claims (1)

Invention Formula Device for determining the completeness properties of logical functions according to auth.St. No. 1170446, which is different from the fact that, in order to increase the reliability of control of the input information, the device contains the fourth and five binary counters and accumulating adder, and the counting input of the fourth counter is connected to the output of the ninth And element, the counting input of the fifth counter is connected to the output of the sixth And element, the information inputs of the accumulating adder are connected to the corresponding outputs of the first binary counter, the census input of the accumulating adder is connected to the output of the second delay element, the outputs setting the fourth and fifth of the binary meters and the accumulating adder are connected to the device reset input, and the outputs of the fourth and fifth binary meters and the accumulating su MmaTors are, respectively, outputs information on the coefficients of non-self-non-monotonicity and non-linearity of the device. Circulation 673 Underworld