SU1287196A1 - Device for determining coefficients of decomposition of correlation function in terms of system of orthonormalized basic functions - Google Patents

Abstract

The invention relates to specialized computer hardware and can be used in the classification of analog signals. The aim of the invention is to improve the accuracy of determining the coefficients of the expansion of the correlation function from systems of orthonormal basis functions of a set. The device comprises an amplifier 1, a scale amplifier 7, a block of aperiodic filters, a group of integrators 4, a block 5 of subtraction, a group of 6 amplifiers, a block 9 of control, an integrator 10, an analog-digital converter 11, a scale-sum block 14, two scale blocks 3, 13, a multiplexer 8. The operation of the device is based on decomposing the correlation function in terms of the original basis of the exponential functions and recalculating the coefficients of decomposition into a new basis based on the conversion factors stored in the memory block and the corresponding parameters. azovany performed by .v device. 5 il. (L

Description

1C

00

with

Od

figure 1

1-12

The invention relates to specialized computational tools for measuring the characteristics of random signals, and can be used in classifying analog signals based on determining the decomposition coefficients of the correlation function of the signal under investigation according to basic systems of orthonormal dial signals.

The purpose of the invention is to improve the accuracy of determining the coefficients of the expansion of the correlation function on the basis of a set.

The operation of the device is based on the representation using the initial basis of the orthogonal functions I g (t) j (I 1,2, ..., L) of the correlation function of the random signal x (t) R (T) with a given error (determined by the number L) in the form of a limited range:

R.C) fl Rfg, (rr).

-t- L

(one)

the system is orthogonal on the interval Q; exponential functions

m

g. (t) E:

g ,, e

(2)

where, i cij, j, rjj A | g dtj (g is the time scale,, d, are tabular coefficients),

The coefficients Rj (B 1,2, ..., L) are determined in accordance with the formula t

I

Rt j-Rx (f)) d t. (3)

For the original basis t

Rt II g ,. Hi,

j-i

Where

t, h, (t) dt-gi. (five)

45 current of the current (UFD), first, p-th, P-th analog switches 17-19 (P - the number of keys corresponding to the number of current discharges of the value T), the input resistor UPT 20, capacitors 15

. . Lf SD / IL. llfJ, Vr-IliVr SL I. J Ul I- mG

MX is the mathematical expectation of the case “-

and bins and 21 feedback, INPUT resistor

npt-nnnTTonriaJU (-sfg

process.

/ t) J 5i. ±) J .2 .... I.

(6)

22 and the UFC 16 feedback circuit resistor 23 (the last transmission coefficient is 1), the first, pth, pth resistors 24, 25, 26, filter input 27, code For the Sth dialing system 55 RUPPA input 28 filter output 29 basis filter.

Scale block 3 consists of L

ir (sm (b ... f-sn (t), scale amplifiers with adjustable ffl 1,2, ..., M. (7) transfer coefficient and register.

Decomposition coefficients are

. T ()., ..., M (8)

Equality is not difficult to convert to mind

   .

When using the original basis

L.

R,

Sm

 / G "i-r

Ji

where

smj

Smi Zl ZI I l

(ten)

(eleven)

0

The values of RS, (S 1,2, ... S, m 1,2,..., M, j 1,2, ..., L) can be calculated on the basis of (11) in advance and stored in memory block ti.

Figure 1 shows the structural diagram of the device; figure 2 - structural diagram of the aperiodic filter;

5 in FIG. 3 is a diagram of a scale amplifier; figure 4 - scheme of the scale unit; figure 5 - structural diagram of the synchronizer,. The device (Fig. 1) contains a littel 1, a block 2 of aperiodic filters, a first scale block 3, a group of 4 integrators, a block 5 of subtraction, a group of 6 amplifiers, a scale amplifier 7, a multiplexer 8, a synchronizer

5 9, an integrator 10, an analog-to-digital converter (ADC) 11, a memory block 12, a second scale block 13, and a scale-sum block 14.

The Black 2 aperiodic filters consist of a set of L aperiodic filters with tunable time constants. Each of these filters can be made containing (Fig. 2) amplifiers 15 and 16 post-amps current (UFD), the first, pth, Pth analog switches are 17-19 (P is the number of keys corresponding to the number of current bits values T), the input resistor UFT 20, capacitors 15

 Lf SD / IL. llfJ, Vr-IliVr SL I. J Ul I- mG

about" -

The specified amplifier contains (fig.Z) analog switch 30, amplifier 31, multiplying digital-to-analog converter 32, analog adder 33, sign input 34 of amplifier, input 35 of amplifier, group of code inputs 36 of amplifier (without sign input), output of amplifier 37.

L-scale amplifiers and register form a block 3 in accordance with the block diagram (figure 4), containing the first, j-th, L-th scale amplifiers 38, 39, 40, register 41, group L of the inputs 42 of block 3, code group N inputs 43 of block 3, control input 44 of block 3, group L of outputs 45 of block 3. The number N of inputs of the code group of block 3 (binary bits of a variable code x (t) is determined by the required accuracy of the representation of the indicated function.

Block 9 is made in accordance with the block diagram (figo5) containing the start device 46, delay element 47, time setting unit 48 T, decimal code converter 49 to binary-decimal code, register 50, triggers 51 and 52, And 53, clock generator 54, master oscillator 55, delay element 56, trigger 57, code comparison device 58, binary-decimal counter 59, node 60 containing the series-connected And element and amplifier, command code generation unit 61, node 62, containing successively connected element And and mustache Operator, node 63, containing serially connected OR element and amplifier, node 64, containing serially connected element I.and amplifier, delay element 65, pulse shaping control unit 66, multiplexer address generation unit 67 pulse shaping unit 68 records in registers, trigger 69 with a counting input, source 70 reference (reference) voltages, pulse control signals forming unit 71, memory block address codes generating unit 72, pulse control units forming unit 73 signal, stop signal generation device 74, node 75 containing AND connected to amplifier and amplifier, Reset signal 76, output 77 group of time interval values T, integrated resolution output 78

output 79 clock pulses to control the operation of the ADC, output 80 write pulses to the register of block 3, output 81 binary codes of the multiplexer addresses, output 82 write pulses to block 12, output 83 of the reference unit voltage, group of outputs 84 write pulses to the amplifier registers 7 and blocks 13 and 14, the output of 85 read pulses from block 12, the output 86 of the binary codes of the addresses of block 12.

The device works as follows.

The signal Xi (t) 1 / T x (t) formed at the output of amplifier 1 is then fed to the inputs of the integrator 10 and block 2 and through multiplexer 8 to the input of A1 Щ 11, where the samples selected in accordance with the Kotelnikov theorem are converted to binary codes.

x

setting at the corresponding times in the amplifiers of the block 3 transmission coefficient values corresponding to the values of the samples. At E. THOM, at the outputs of blocks 2-4, 10 of the device, signals appear correspondingly:

 f V4) M ..; M. 5 -; - ile

2j

1 1 T J l, ii, ..., b,

(12)

x

,, (t) X2. (t) k 0,1,2, ... K;

 j j i

(13)

x

, (t) x, (t) dt; j 1,2, ... L; (14)

(15)

x, (t) r5Mdt.

about

After the end of the integration resolution signal (at the time t t), the integrators of the block 4 and the integrator 10 voltages t

4j

(T) J Xs. (t) dt; j 1,2, ... L; (sixteen)

(T)

-and.-4-J

x (t) dt.

(17)

30 x 45 50

The voltage (17), taken from the output of the integrator 10, through the multiplexer is fed to the input of block 11, where it is converted into a binary code, which 55 is written to the register of the amplifier 7, setting the corresponding transmission coefficient in it. The output voltage of the amplifier 7 in this case is proportional to the value:

(18) block 6 is converted

j 1,2, ... L

in tension

Mi

v -, l

b Pi

Then at the outputs of block 5 there are signals proportional in magnitude to the magnitudes:

(nineteen)

H.j

x, x ,, (T).

J 1,2,. /. L. (20) The values (20) are converted in block 1 1 into binary codes, which are then written into the registers of block 13 (with the continuous numbering of registers, into registers from the second to (b + 1) -th registers). In this case, the L outputs of block 13 contain voltages proportional to the values of Hj (j 1,2, ... L). Based on them, for each S-ro basis (S 1,2, ... S) and every t-th component (m 1,2, ... M) in block 14, M-S decomposition coefficients RS are determined the correlation function R (t) of the random process x (t in accordance with formula (10). At the same time, for every $ 1.2, .., S, and ha, 1.2, .., L operations are performed when 12 is read and written into the corresponding registers of the block 14 of the L binary codes of the value Rshi: then the binary code of the value Rjh is written to the block 12. The output voltage of the I4t block

Claims (1)

Invention Formula A device for determining coefficients of decomposition of a correlation function from an orthonormal basis function system, comprising an amplifier, a scale amplifier, an aperiodic filter unit, an integrator group, a subtraction unit, an amplifier group, an integrator, an analog-to-digital converter, a memory block, a scale-sum block, and the information input of the amplifier is the input of the device, and the output is connected to the input of the aperiodic filter unit, the output of the scale amplifier is connected to the input of the amplifiers of the group, the output is tax-to-digital converter connected to the information input a memory block, the output group of which is 55-mTel and with the integrator output connected to a group of information inputs of a scale-summing block, characterized in that, in order to improve accuracy, it is Two scaled blocks, a multiplexer and a synchronizer are given, the scale amplifier contains an amplifier, a digital-to-analog converter, an adder, a key whose control input is the input of a sign bit of the group of the digit inputs of the gain code of the scaler, the information input of the connectors key with the first input of the adder and the output of a digital-to-analog converter, the information input of which is the information input of a scale amplifier, a coefficient setting input The 5th transmission of the digital-to-analog converter is the input of a group of significant bits of the group of bit inputs of the gain code of the scale amplifier, the key output is connected 0 through the amplifier with the second input of the adder, the output of which is the output of the scale amplifier, the first scale block contains a group of scale amplifiers and a register, the group 5 information inputs of which is a group of bit inputs of the transfer coefficient code of the first scale unit, a register write enable input is an input of the write resolution of the first scale unit, the register bit outputs are connected to the corresponding bit inputs of the transfer code of the scale amplifiers of the group, infor5 The matrix inputs and inputs of which are a group of information inputs and outputs of the first scale unit, respectively, the second scale unit contains a group of scale elements - 0 drivers and a group of registers whose recording resolution inputs are a group of recording resolution inputs of the second scale unit, the bit outputs of the group registers are connected to the 45 bit inputs of the transfer code of the corresponding scale group amplifiers, the information inputs of the group scale amplifiers are the input unit reference - the 50th voltage of the second scale block, and the inputs are the outputs of the second scale block, with the output of the scaling block, with the information input of the scale block ivhod coupled to an output amplifier with a group subtracting unit outputs aperiodic band filterbank outputs is connected with the group. 712871 information inputs of the first scale block, the group of bit inputs of the transfer coefficient code of which is connected respectively to the groups of bit inputs of the coefficient code. the transmission of the second scale unit, the scale amplifier and is connected to the output of the analog-digital conversion. 968 body, a group of outputs of the first scale block is connected to a group of inputs, integrators of a group, a group of outputs of which is connected to the first group of inputs of a subtraction unit: the second rpjmna of which inputs are connected to the outputs of the corresponding groupers of the group. 23 (Pus. 2 )eleven --- Li J ffl J P fS FIG. if