SU1695323A1 - Digital filter - Google Patents

Abstract

The invention relates to automation, computing and measuring technology and can be used in the processing of stationary (non-Gaussian) signals, for example, in data compression and image processing systems, correlation and spectral analysis, etc. The purpose of the invention is to expand the field of application by determining the statistically stable number of zeros of high orders of repeated-difference and repeated-total signals. The goal is achieved due to the fact that the device includes a centering unit 1. counter 2. M + 1 (M is the filter order) of computing blocks 3.1-Z.M + 1, the first of which contains analog-to-digital converter 4, and the subsequent ones are the buffer register 5 and the adder 6, with each computing unit including a random number generator 7, a comparison node 8, pulse formers 9, 10, 11 .. an element OR 12. a counter 13 and a buffer register 14. 1 Il.

Description

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The invention relates to automation, computing and measuring technology and can be used in the processing of stationary (non-Gaussian) signals, for example, in data compression and image processing systems, correlation and spectral analysis, etc.

The purpose of the invention is to expand the field of application by determining the statistically stable number of zeros of high orders of repeated-difference and repeated-total signals.

The drawing shows the functional scheme of the digital filter.

The digital filter contains a centering block 1, a counter 2 (implementation interval), M + 1 computational blocks 3.1-3.M + 1, (M 2), the first of which contains analog-to-digital converter 4 (ADC), the second and subsequent ones (input ) buffer register 5 and adder 6, each

from computational blocks Z.K. (K 1) contains 7 random number generator, node 8 comparison, pulse formers 9-11, element OR 12, counter 13 (pulses), (output) buffer register 14, information 15, clock 16. inputs , outputs 17.1-1-17. (M + 1) digital filter.

The digital filter works as follows.

The input analog signal is fed to the information input 15. In block 1, the constant component is removed from the input signal and the signal spectrum is corrected simultaneously with the suppression and underlining of individual frequency bands. In each block Z.K. (K 1), for a time equal to the implementation interval and determined by the sampling frequency T and the N division factor of counter 2, the number of zeros of the k-th order of stationary (non-Gaussian) is determined

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centered input: in the first block 3.1 - the number of intersections of the input signal of a random curve, in the second block 3.2 - the number of intersections of the first derivative of the input signal of a random curve, in the third block 3.2 - the number of intersections of the second derivative of the input signal of a random curve, etc. The random curves in blocks 3.1-Z.M + 1 are statistically independent. At the end of the implementation interval (s), the indicated values are written into the output buffer registers 14 of block 3 and are fed to outputs 17.

This is done like this.

From input 16 to the clock input of counter 2, a continuous sequence of pulses arrives, whose frequency T is equal to the sampling frequency of the input signal and determines the resolution of the digital filter and the accuracy of determining the number of zeros of high orders of the input signal. In block 3.1, the centered input signal is sampled and quantized at a frequency using ADC 4, the outputs of which form the sign and the absolute value of the input signal according to the rule

pWm EMmENT (i, + 0,5), (1)

where Pwm is the numerical value of the input signal reference;

 - his sign

Hm - counting the input signal at the time of sampling,

S min - the minimum non-zero quantization step,

ENT (.) - the whole part of the value (.).

The quantizing characteristic of the ADC 4, according to (1), corresponds to the quantizing characteristic with central suppression of weak signals.

The random number generator 7 generates from the pulses from clock input 16 a sequence of random numbers {rm}, the range of which corresponds to the range of change of the quantized signal {Pm} from the output of the A / D converter 4. Comparison node 8 compares the values and 2t, and The output of node 8 generates a signal of a logical unit, and when a signal is a logical zero. During the implementation interval (s) in the first block 3.1, using the comparison node 8 and counter 13, the number of intersections of the input centered signal of the random curve {2 tons} of the output change of the comparison node 8 from one to zero and from zero to

unit. At the end of the implementation interval I), on the leading edge of the pulse from the output of counter 2, the contents of counter 13 are recorded in register 14, and counter 13 is zeroed,

those. prepared for the next accumulation cycle. Thus, at the outputs of register 14 bpock 3.1, the number of zeros of the first order of the centered input signal is formed, which is stored on

these outputs during the next implementation interval,

The formation of the number of zeros of the K-th order (K 2) of the centered input signal is considered on the example of block 3: k (k 2).

The sequence of readings {pnp} coming from the outputs of the A / D converter 4 is gated in register 5 of block 3.2, as a result of which during the sampling period T the inputs and outputs of this register 5 contain the values P t and P x t-t arriving at the inputs of the adder 6 The adder 6 performs the subtraction (when operating in the additional code) of the Pt-1 value from Pt, i.e. re-subtract operation

 y - pM p (x) VAm - g m rv m-i,

which at k 2 corresponds to the formation of the first difference of the sampled and quantized centered input signal. At the same time, the generator 7 from pulses from clock input 16 generates a sequence of random numbers {22 tons}, the range of which corresponds to the range of variation of the first difference {vXm} from the output of the adder 6. When

Assistance of node 8 compares the values of Xm and 2 m, and when the condition at the output of node 8 is formed, a signal of a logical unit is generated, and at Xm 1m a signal of a logical zero.

The change in the output signal of the comparison node 8 (from zero to one and from one to zero) is counted by counter 13 during the implementation interval (recorded by a signal from the output of counter 2 at the end of the realization interval in register 14, and counter 13 is zeroed, preparing for a new cycle Thus, at the outputs of register 14 of block 3.2, the number of zeros of the second order of centered

input signal (the number of intersections by the first difference of the input signal of the random curve {2m}, which is maintained at these outputs during the next implementation interval.

5Blogs З.к (к 2) work in the same way,

performed the difference operation V V (Vk 2 Xm) Xm Xm-1, and counted the number of intersections by the signal {v7k Xm} of the chance curve {2n / k} over the implementation interval).

Therefore, at the outputs of the output buffer register 14 (outputs 17.c) of the block Z.k, the value of the number of zeros of the stationary (non-Gaussian) centered input signal K-ro is formed, which is stored at these outputs during the next implementation interval. At the outputs 17.K + 1, a recurrent difference signal (k-1) of the order of Xm} is formed.

When repeatedly summarizing the signal processing, the adders 6 of the computational blocks 3.1-Z.M + 1 work with numbers in a direct form, i.e. in the summation mode.

When the generator generates 7 random numbers of a sequence of zeros (which is equivalent to its joint with the comparison node 8 exclusion from the circuit with a direct connection of the inputs of the formers 9.11 with the output of adders 6 or ADC 4, the number of zeroes will be determined without statistical stability of the results.

Claims (1)

Invention Formula A digital filter containing a centering unit, a counter and M + 1 (M is the filter order) of the computational units, the first output of the 1st (1 1, M + 1) computing unit is the i-th information output of the filter, the second j-roQ output 1, m) of the computing unit is connected to the information input of the 0 + 1) computing unit, the information input of the first computing unit is connected to the output of the centering unit, the input of which is the information input of the filter, the first clock inputs of all computing units are connected to exit transfer account The counting input of which is connected to the second clock inputs of all computing blocks and is connected to the filter clock input, with the 1st computing block containing three pulse shapers, the OR element, the counter and the first buffer register, whose information input is connected to the information output of the counter , the counting input of which is connected to the output of the element OR, the first 0 five 0 five 0 5 0 5 0 and the second inputs of which are connected to the outputs of the first and second pulse formers, respectively, the zeroing input of the counter is connected to the output of the third pulse shaper, whose input is connected to the clock input of the first buffer register and connected to the first clock input of the computing unit, the first output of which is the output of the first buffer register, with the k-th (K 2, M + 1) computing unit additionally contains an adder and a second buffer register, the output of which is connected to the first input of the adder, the second the input of which is connected to the information input of the second buffer register and connected to the information input of the computing unit, the second output of which is the output of the adder, the clock input of the second buffer register is the second clock input of the computing unit, characterized in that in order to expand the application area by determining the statistically stable number of zeros of high orders of repeated-difference and repeat-sum signals, the random number generator and the node are entered into the i-th computing unit In the first computing unit, the output of the random number generator is connected to the first input of the comparison node, the output of which is connected to the inputs of the first and second pulse shapers, and the clock input of the random number generator is connected to the first computing unit. to the second clock input of the computing unit, with the output of the analog-digital converter in the first computing unit connected to the second input of the comparison node and the second output of the computing unit, to inf The memory input of which is connected to the information input of the analog-digital converter, the clock input of which is connected to the second clock input of the computing unit, in which computer unit the output of the adder is connected to the second input of the comparison node. 17.2