SU1283797A1 - Device for translating codes from one language to another - Google Patents

Abstract

The invention relates to computing and can be used in systems for implementing high-level languages, instrumental translators, emulators and interpreters. The aim of the invention is to extend the functionality by ensuring that the operation of restricting relational algebra is performed. The device contains a memory block, a receive register, a issue register, an address register, a buffer register, two modulo adders, an OR block, a trigger trigger, a clock generator. 1 il.

Description

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The invention relates to computing technology and can be used in control systems of relativistic databases, in systems of direct implementation of high-level languages, in instrumental translators, emulators and interpreters.

The purpose of the invention is to expand the functionality by ensuring the execution of the operation of restricting relational algebra.

The drawing shows the functional diagram of the device.

The device contains a memory block 1, a reception register 2, an address register 3, a buffer register 4, a output register 5, a modulo-2 block 6, a modulo-two block 7, a block of 8 OR elements, a trigger trigger 9, a clock generator 10 pulses, information input 11 of the device, input 12 of the start of the device, input 13 of the conversion conditions, output 14 of the device.

The device works as follows.

: In the initial state, the memory elements of the device are in the zero state (with the exception of the bit; the issue register defining the sign of the end of the process of converting the input word to a certain set, including zero, output words),

The input word arrives at the information input 11 of the device and is entered into the receive register 2. At the same time, the input word consists of two half words: one - directly for conversion into the output word sequence, the other - for organizing the operation of restricting the relational algebra. The operation of the device begins when a pulse arrives at the input 12, which translates the trigger trigger 9 into a single State. The potential of a logical unit at the control input of the generator 10 permits the generation of clock pulses at its outputs. The generator 10 impulse arrives at (the synchronization input of the address register 3, the input word is rewritten from the first floor to the reception register 2 via the block 8 elements OR to the address register 3. This will form the initial address of the program

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we convert the input word to a set of output words.

Memory block 1 stores both the output words and the addresses of the next output words after the previous output word.

When issuing the next clock pulse from the output of the generator 10, the first output word of the conversion program is entered into the buffer register 4. The address of the next output word is set either explicitly with a linear sequence of words or indirectly, when the address depends on the conversion conditions. The code of the condition being tested, which determines the path for further conversion, is specified in the first field of the buffer register 4. Directly the address is modified on the modulo-two adder block when the code of the transformed condition is modified by the conversion conditions from the device 13. On the next clock pulse, the output word from buffer register 4 through block 7 is entered into output register 5. From the output register 5, the generated output word enters the output 14 of the device.

If the input word matches exactly one output word, i.e. If the one-to-one I conversion mode is performed, then simultaneously with the output word, a label indicates that the conversion process is complete. This label zeroes the trigger trigger 9, the address register 3, the boolean register 4 and the issue register 5, and also enters the next input word for conversion (not shown) in reception register 2.

If the next output word is the output word of a linear sequence, then from the output of the buffer register 4, through the block 8 of the NPS elements, the address input of the next output word enters the information input of the address register 3. Further, the selection of information from memory block 1 and the operation of the device occur as described above.

If the next output word is a word, after which the conversion process 55 follows one of the possible paths determined by certain conditions, then the indirect address of the next output word will be read from the floor of the buffer register 4. WITH

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another FIELD buffer register 4 will be read the code of the condition being checked. This code on block 6 is modified by logical conditions from the input 13 of the device. As a result of the modification of the indirect address at the inputs of the register 3, the address of the next word is formed, which determines the further process of converting the words of the input language to the words of the output (including machine) language.

The operation of the device in the implementation of the operation of restriction of relational algebra is similar to the operation of the device in the implementation of the usual list of input words. A distinctive feature is that, if it is necessary to implement the restriction operation, from input 11 of the device, some code is entered into the second field of register 2. Therefore, the read output word from the third floor of the buffer register 4 is modified (modified) by the code from register 2 at block 7 modulo-two adders. As a result of the modification, the output word is fed to register 5, and then to output 14 of the device.

Thus, the device allows the exclusion of a word from the output sequence, for example, provided that the specified relation between the given letters of the word is not fulfilled.

Claims (1)

Formula invented A device for converting codes from one language to another, containing a memory block, reception register, a register, an OR block, the first block of modulo-two adders, a buffer register, an address register, a trigger trigger, a clock generator, and a trigger input is connected to the single trigger trigger input, the single output of which is connected to the control input 5 o 0 thirty 35 40 45 974 clock pulse, the first output of which is connected to the synchronization input of the address register, the output of the address register is connected to the address memory block, the information input of the device is connected to the input of the reception register, the output bits of the first floor of which are connected to the first input of the block of elements OR, output. a block of elements OR is connected to the first information input of the address register; the input of the device conversion conditions is connected to the first input of the first modulo-two block, the output of which is connected to the second the information input of the address register, the second output of the clock generator is connected to the synchronization input of the buffer register, the third output of the clock generator is connected to the synchronization input of the output register, the information output of which is connected to the output of the device, the output of the indication of the end of the process of converting the output register is connected to the zero trigger input , characterized in that, in order to extend the functionality by ensuring the implementation of the operation of limiting rel the second block of modulo-two adders, the output of the memory block is connected to the information input of the buffer register, the bits of the first field of which are connected to the second input of the first block of modulators, two, the outputs of the bits of the second floor of the buffer register connected to the second input of the block of OR elements, the outputs of the bits of the third floor of the buffer register are connected to the first input of the second block of adders modulo two, the second input of which is connected to the output i and the bits of the second floor of the register The receiver, the output of the second block of modulo-two adders, is connected to the information input of the register.