SU1238104A1 - Device for translating codes from one language to another - Google Patents

Abstract

The invention relates to computing. The aim of the invention is to reduce equipment. The device contains a memory block 1, a group of 2 memory blocks, an address register 3, a register 4, an address switch 5, a multiplexer 6, a trigger 7, a clock generator 8, a one-shot 9, delay elements 11, 11, a data input 12, an input 13 start-up of the device, input 14 conditions and output 15 of the device. 1 il. (L

Description

The invention relates to computing technology and can be used in systems of direct implementation of high-level languages, instrumental translators, as well as in systems with interactive development, debugging and program execution, emulators and interpreters.

The purpose of the invention is to reduce equipment.

The drawing shows a diagram of the proposed device.

In the drawing, the following designations are accepted: memory block 1, group 2 memory blocks, address register 3, output register 4, address switch 5, multiplexer 6, trigger 7, generator 8 clock pulses, single vibrator 9, ele; cops 10 and 11 delays, information input 12, device start input 13, condition input 14 and device output 15.

Group 2 of memory blocks is designed to store information about individual syllables of output words. Storing the syllables of the output words in separate memory blocks makes it easier to adapt to new input algorithmic languages, since the transcript (words of the output language) are stored as objects — clusters, represented by some kind of abstract data. In this device the orthogonal is realized. a two-level, two-channel) conversion control process. In the first channel, addresses are managed, in the second, output words are formed directly from individual syllables.

. Multiplexer 6 is designed to form the value of a modifiable address bit of the next address word and implements the following logic function:

y, “Xja + y, z, ... x, z, where y ,, is the output signal of the multiplexer 6 ;.

X, is the conjunction of ,, oZj corresponding to the code from the output of memory block I (the code of the transformation conditions), allowing resolution; modified address bit and no change ;; :

X 2 l, ei d. «Ы X j (Xi-Oij,.. .Ot} X

S, ot, t, (it,, .l - conjunctions corresponding to the codes defining the transmission 1238104. 1

output to multiplexer 6 of one of the conversion conditions

h

five

0

five

0

five

0

five

0

five

. .. z, with input 14 conditions. The address switch 5 is intended for switching either the first address word corresponding to the conversion process of the incoming input word or the next address word.

The operation of the device is as follows.

In the initial state, the memory elements of the device are in the zero state. The device starts working when a start signal arrives at the input 13 of the device. This signal arrives at the single input of the trigger 7 and sets it to the single state. The logic unit signal from the output of trigger 7 permits the passage from input 12 of the input word to convert it to some set of words in the output language. The input word through the switch 5 is fed to the input of the register 3 addresses and at the end of the first clock pulse is entered into the register 3 addresses. Thereby, the address of the first address word is formed in the block 1 item. According to the address of the word, which is in the 3 address register, the addresses of the syllables of the first output word are computed by the first clock pulse from memory block 1 (when the One mode is implemented in several). The clock pulse of the output of the generator 8 at these addresses is used to sample information from group 2 of memory blocks. And by the same clock pulse delayed on the delay element 11, the selected information is output in the output register of the word into the output register 4 and from its output goes to the output 15 of the device 15.

The next output word can be either the output word of a linear sequence of words, or its address depends on certain conditions defined by the conversion process. In addition, the One-to-One conversion mode is possible in which one input word corresponds to each input word. When this mode is implemented simultaneously with the addresses of the syllables of the output word, a label is displayed - a sign of the end of the conversion from the output of memory block 1. This label - a sign is fed to the input of the one-shot 9, the output to

Secondly, a pulse is formed, zeroing trigger 7, thus the device is ready to receive the next input word. If the next output word is the output word of a linear sequence, then from the output of memory block I to the input of switch 5 the address receives the code of the next address word, which selects and forms the next output word similarly to the specified one. If the next output word is a word, after which the conversion process follows one of the possible paths determined by certain conditions, then from the code of memory block 1 to the input of multiplexer 6, the conversion condition code (its constant - unmodifiable part) C the output of memory block 1 also receives a modified bit. The code of the transformed condition to be tested on multiplexer 6 is modified by conditions coming from the input of 14 conditions. If the condition being tested changes (modifies) the bit, then the output of multiplexer 6 is a logical unit1 signal, which supplements the address of the next address word and thereby changes the branch of the transformation. The code of the next address generated in the image is sent through the address switch 5 to the address register 3 J and the device continues its operation. With the output of addresses of the syllables of the last output word from the output of memory block I, a label is displayed - a sign of the end of the conversion. This label through the odovibrator 9 zeroes trigger 7 and thereby prohibits the generation of pulses. The device is ready to receive the next input word.

Claims (1)

Invention Formula A device for converting codes, from one language to another, containing a memory block, the address input of which is connected to the output of the address register, trigger, a group of blocks pa. ten 15 20 five five 0 five 0 mi, the register, clock generator, the first output of which is connected to the synchronization input of the address register, the single trigger input is the device start input, the single trigger output is connected to the clock generator input, the outputs of the group memory blocks are connected respectively to the register information inputs output, the output of which is the output of the device, characterized in that, in order to reduce the equipment, it contains two delay elements, a one-shot, an address switch and a multiplex the output of which and the output of the non-modifiable address bits of the memory block are connected to the first information input of the address switch, the second information input of which is the information input of the device, the output of the address switch connected to the information input of the address register, the input of the device conditions connected to the first information input multiplex -: ra, the second information input of which is connected to the output of the modified bit address of the memory block, the output of the condition code of which is connected to the authorizing input of the multi the output of the syllable addresses of the memory block is connected to the address inputs of the memory blocks of the group whose synchronization inputs and the input of the first delay element are connected to the second output of the clock generator, the output of the first delay element is connected to the synchronization input of the register register, the input of the second delay element connected to the first output of the clock generator, and the output connected to the synchronizing memory block, the output of the sign of the end of the conversion of the memory block is connected to the prohibitory input of the switch ora addresses and input odnovibrato- pa, whose output is connected to the zero input of the trigger unit output is connected to the enabling input of the switch.