SU1282344A1 - Device for generating audio information packages - Google Patents

Abstract

The invention can be used in digital communication systems and provides a reduction in packet forming time. Speech information from input 16 passes to speech analyzer 1 and non-cutter quantizer 2 to encoder 4. Speech analyzer 1 output signal gates quantized pulses and clock pulses 1 received through Elements 3.5 of the frequency divider 6 and reference oscillator 7 The coded signal with a clock frequency F is fed to the distributor 8, which alternately connects the packet registers (7P) 9,10 to record and form packets. The presence of two DFs allows the parallel processing of two packets and the matching of packets passing through the combining unit 15 to the output 21, with a clock frequency FF). The signals controlling the recording process and the sharing in the DL 9 and 10 come from the block 11 logic. The logic block 1I is entered into RP 9 and 10 codes, which at each current time are in register 12 of the time code, in register 13 of the code length, in register 14 of the address code. Introduced the second RP 10 and distributor 8. 2 Il. i (L

Description

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The invention relates to time-compressed devices in digital packet-switched communication systems, in particular in telephone information transmission networks.

The aim of the invention is to reduce the formation time of the packets.

Figure 1 shows a block diagram of a device for forming voice information packets; 2, implementation of a logic block is possible.

The device for forming voice information packets (Fig. 1) contains speech analyzer 1, quantizer 2, first element 3, encoder 4, second element 5, frequency divider 6, reference generator 7, distributor 8, first register 9 of packets, second register 10 packets, logic block 11, time code register 12, code length register 13, address code register 14, combining unit 15, first device input 16, second device fifth inputs 17-20, device output 2.

Block 11 logic (figure 2) contains the first inverter 22, the first - the third keys 23-25, the first driver 26, the first element ShZh 27, the second element OR 28, the first - the third trigger 29 - 31, the fourth - the seventh keys 32 - 35 , the first counter 36, the third element OR 37, the second counter 38, the second driver 39, the fourth element OR 40, the second inverter 41, the fifth element OR 42, the fourth trigger 43, the third inverter 44, the fifth trigger 45, the first switch 46, the sixth and seventh elements OR 47 and 48, the eighth - eleventh keys 49 - 52, the second switch 53, the eighth and ninth elements OR 54 and 55.

The proposed device works as follows.

The speech information from the first input 16 of the device enters the speech analyzer 1 and the quantizer 2. The speech analyzer 1 evaluates the difference in the presence or absence of a speech signal and generates an output signal that determines the presence of speech. The device provides for adaptive quantization of speech signals depending on the load in the linear paths, i.e. it is possible to vary the quantization rate of the incoming signals. The quantizer 2 is controlled by the reference

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generator 7 with a variable clock speed, and the output signal is determined on the first element And 3 after dividing the frequency of the clock pulse in the frequency divider 6. The output of speech analyzer 1 gates quantization pulses. The encoder 4 receives the clock pulses from the code of the second element 5, whose input is also gated by the output signal of the speech analyzer 1. The input of the second element And 5 also receives a sequence of pulses from the output 5 of the reference oscillator 7. Thus, the encoder 4 is clocked with a higher frequency than the quantizer 2. This makes it possible to encode each sample in the form of a code group using any algorithm.

The output signal of the encoder 4 is inputted to B, the distributor 8 with a write clock frequency F coming from

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element And 5. The distributor 8 connects alternately shear first and second registers of packets 9 and.

10 write and package. The presence of the first and second registers .9 and 10 allows parallel processing of two packets and read them without extensive rewriting.

on the output 21 of the device, ready-made packets with a read clock frequency FjCFj). At the point in time, when in the first register 9, a packet is written and formed (n + 1), in the second register 10 the nth packet is read. The header code is written in parallel form directly into the first and second registers 9 and 10 before the formation of the information part of the packet begins. The signals controlling the writing and reading process come from the block.

11logiki. Reading the information (the transmission of the packet to the communication channel should be faster than recording, because otherwise information may be lost.

The logic unit 11 enters into the first and second registers 9 and 10. codes that are currently in registers 12 - 14 at each current time. Register 12 contains a time indication code that comes from the second input 17 of the device. Codes-and-time information represents the current time determined by reference oscillator 7.

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The I3 length code of the speech interval regulates the rate of quantization of the speech signal depending on the load, thereby determining the length of the information part of the packet. Register 14 contains packet address codes.

When the equipment is turned on and the transients end, the device for forming voice information packets will be set to wait for voice intervals.

If after the end of transients the fourth trigger 43 is set to the logical state O then the first register 9 will be in the initial state in the parallel recording mode, the second register 10 will be in the information shift mode.

The modes of operation of the first and second registers 9 and 10 are given by the potentials taken from the outputs of the sixth and seventh elements OR 47 and 48, respectively.

When a speech signal appears, speech analyzer 1 generates a speech interval signal that sets the first trigger 29 to the logical 1 state, opens the second and seventh keys 24 and 35, and the second switch 53.

The header code of the first packet from the registers 12-14 through the second switch 53 in parallel form is a post to the inputs of the first and second registers 9 and 10. On the leading edge of the same signal, the second driver 39 generates an impulse which in the first register 9 The header code of the first packet is stored. The same impulse will transfer the fourth trigger 43 to the opposite state: logical 1. The first register 9 will be set to the information shift mode, and the second register 10 - to the parallel recording mode.

The impulse generated by the shaper 39 through the open second key 24 enters the input of the third trigger 31 and sets it to the logical state 1. The sixth key 34 opens and the clock frequency FJ starts to enter the second count 38, and through the eleventh open key 52 the second register 10, which was set to parallel record header, the second packet.

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The signal from the third trigger 31 also opens the first switch 46, and the code from the register 13 goes to the control inputs of the encoder 4 and the reference generator 7. Through the open fourth key 32 to the input of the first counter 36 and the clock input of the first register 9 clock pulses arrive F. In synchronization with the clock pulses, the information input of the first register 9 enters information from the encoder A. Thus, in B the first register 9 the first packet with the clock frequency F is formed.

When the first counter 36 counts the maximum length of the information part of the first packet, it generates a packet shaping end signal, which sets the fourth trigger 43 to the logical O state, and the fifth trigger 45 - to the logical 1 state and resets the first and second counters 36 and 38 while the first register 9 is completely filled. Now the clock frequency F (F,,) starts to flow through the open ninth key 50 to the synchronization input of the first register 9, and the clock frequency F through the open tenth key 51 to the synchronization input of the second register 10, and both registers are set to shear.

Since the first register 9 is completely filled and is in the shift mode, when the clock frequency F arrives, the first packet of voice information will start coming from its output to the device output 21.

While information is being read from the first register 9, a second packet is formed in the second register H, since the potential from the seventh element OR 48 is set to the shift mode and informational signals and clock signals synchronously arrive at its information input and synchronization input. FJ frequency, respectively.

When the second counter 38 counts the length of the first transmitted packet, Loth consists of a header and an information part, and an ending pulse is generated in it.

Get out the packet that sets the fifth trigger 45 to the logical O state. The first register 9 switches to parallel-write mode and the third packet header code is written to it.

When the second packet is formed and the first counter 36 counts the length of the information of a part of this packet, it will generate a pulse to terminate the formation of the packet, which will transfer the fourth trigger 43 to the logical state 1. The first register 9 will be set to the formation mode of the third packet with a clock frequency F, and The second register 10 at the device output 21 will start reading the second packet with a clock frequency of FJ.

The processes described will be repeated until a pause occurs. When a pause occurs, the first key 23 opens and the second switch 53 terminates. The first counter 36 counts the maximum length of the last packet (the missing bits of the last packet are filled with zeroes) and a pulse of the end of the formation of the packet that sets the second and n The triggers 30 and 45 are in a state of logical O, and the fourth trigger 43 is in the opposite state. Thus, the reading of the last written packet to the output 21 of the device from one register and the formation of the empty packet in the other will begin.

If the pause ends before the arrival of the end of the packet readout from the second counter 38, the second trigger 30 is set to the logical 1 state and everything is described. The processes are repeated.

If the pause lasts longer and the second counter 38 counts the maximum length of the last transmitted packet, it will generate a pulse to read the packet, which sets the first and third triggers 29 and 31 to the logical state. The device will go to standby mode.

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Claims (1)

Invention Formula A voice packet generator that contains 5 consequently connected quantizer and encoder, as well as a speech analyzer, the input of which is connected to the first input of the quantizer, the second input of which is connected to the output of the first 0 element And, the first input of which is connected to the output of the speech analyzer and the first inputs of the logic block and the second element And, the second input of which is connected to the output of the reference generator 5 of the torus, the second input of the logic block and the input of the divider, the output of which is connected to the second input of the first element And , and the output of the second element And is connected to the second input of the encoder, 20 whose third input is connected to the input of the reference generator and the first output of the logic block, the second output of which is connected to the first input of the combination block, the second input of which is connected to the output of the first packet register, and the third, fourth and fifth inputs of the logic block are connected respectively to the register outputs time code, code length register and register25 thirty code addresses whose inputs, and also the sixth input of the logic block is the second, third, fourth and fifth inputs of the device, respectively, characterized in that 35 in order to reduce the formation time of packets, a second register of packets and a distributor are entered into it, the first input of which is connected to the output of the encoder, and the second stroke of the body distribution 40 is connected to the third output of the logic block, the fourth and fifth outputs of which are connected respectively. , the second, and third inputs of the first and second packet registers, the second 45 inputs of which are connected respectively to the first and second outputs of the distributor, the output of the second packet register connected to the third input of the combining unit, the output of which is the output of the device. VjS, lf