SU980281A1 - Binary code-to-time interval converter - Google Patents

Description

The invention relates to a pulse technique and can be used in devices for converting and encoding information computational control and information systems.

A known converter of a code into a time interval, containing a reference frequency generator, connected via an AND element to the counter input, the bit outputs of which through an encoder are connected to the inputs of the matching element, a trigger, one input of which is connected to the counter output, an additional trigger and an And element, one the input of which is connected to the output of the first digit of the counter, another input - with the output of the first element AND and the additional input of the element of coincidence, and the output - with another input of the first trigger, one input The output trigger is connected to the output of the matching element, and the other input is connected to the output of the counter t.

A disadvantage of the known device is the large transform error, equal to the pulse repetition period of the reference frequency.

A known code-to-time converter is used, containing a reference frequency generator, a key, the first input of which is connected to the pulse bus of the beginning of the time interval, a pulse counter, the setup inputs of which are connected to the bus of the code being converted, and the outputs to the inputs of the reference element whose output is connected to the input element And, the element AND-NOT, the first input of which is connected to the output of the key, the second input of which is connected to the output of the pulse counter, the counting input of which is connected to the output of the element AND-НЁ, the second input of the the second is connected to the generator of the reference frequency 112 J.

The disadvantages of the known device are low conversion accuracy due to out-of-sync of the leading edge of the pulse of the start of conversion with the leading edge of the filling pulse, as well as the limited range of time intervals of increased accuracy.

The purpose of the invention is to improve the accuracy of the conversion.

The goal is achieved. Let us say that the binary converter

30 codes in the time interval containing the geirtor of the reference frequency, the key, the first input of which is connected; with the pulse bus of the beginning of the time interval, the pulse counter, the setup inputs of which are connected. to the converted code bus, and the outputs to the inputs of the comparison element, the output of which is connected to the first input of the AND element, the NAND element, the first input of which is connected to the output of the key, the second input of which is connected to the output of the pulse counter, countable

the input of which is connected to the output of the NAND element, the second input of which is connected to the output of the reference frequency generator, a stable high frequency generator7, a reversible counter, an additional comparison element, an additional AND element, an additional NAND element, a trigger, a single installation input of which is connected to bus. pulse of the beginning of the time interval, and the zero output is connected to the summing control input of the reversible counter and the first input of the additional element I, the second input of which is connected to you ode reference frequency generator, and the output - to the input

reset the reversible counter, readout, the control input of which is connected to the first input of the AND element,

the counting input is with the stable, high frequency generator output and the second input of the AND element, and the outputs with the corresponding inputs of an additional comparison element, the output of which is connected to the third input of the AND element, the output of which is connected through an additional 1 AND-NOT element to the pulse counter reset input and

with zero trigger trigger input.

FIG. 1 is shown structurally. The device diagram in FIG. 2 - time diagrams, according to his work.

The device contains a key 1, an element AND-NOT 2, a counter 3 pulses, a generator 4 of the reference frequency, an element 5 of comparison, an element 6, an generator 7 of a stable high frequency, a reversible counter 8, an additional element 9 of comparison, an additional element 10, an additional element AND NOT 11, trigger 12.

  . -. The Converter operates as follows.

In the initial state, a code inverse to the convertible code is entered into the pulse counter 3, the trigger 12 is set to the zero state. Potency-resolving from the zero output of the trigger 12 (Fig. 2aj is fed to the first input of the Additional element AND 10 and to the summing control input of the reversible counter 8, which carries out the summing of the pulses fed to its counting input from the stable high frequency generator Fig 2) . The reversible counter 8 is zeroed by the generator 4 reference frequency pulses, which arrive at the reset input through

 open additional element And 10 (Fig. 2t-). After the end of the action of the pulse generator 4 of the reference frequency, the reversible counter 8 again performs the operation of summing the pulses of the generator 7 of a stable high frequency.

The moment of arrival of the pulse of the beginning of the time interval (fig. To the input of the installation of the key 1 and to the single installation input of the trigger 12 corresponds to the beginning of the time interval. This opens the key

Q 1 and trigger 12 at the leading edge of the start pulse of the conversion are set to state 1 (Fig. 2c | j. The additional element And 10 closes and the reversible counter 8 stops the operation

summing the pulses from the generator 7. Thus, during the desynchronization time of the leading edge of the reference frequency generator with the leading edge of the conversion start pulse, the number of pulses from the stable high frequency generator 7 is remembered on the reversing counter 8.

The pulses from the generator 4 of the reference frequency begin to flow through the element AND-NOT 2 to the input of the counter of 3 pulses, the bits of which change their state at the end of the input pulse (along the trailing edge of the input pulse /. After the N-ro pulse of the reference frequency passes, all the triggers counter 3 wuxi II

tantalized to the state

I- /

at that, the comparison element 5 forms a signal (Fig. 2 c.) arriving at the first input of the element Ib and at the subtracting control input of the reversible counter 8, which performs the operation of subtracting the previously stored pulses until all the triggers of the counter 8 are set to the state Oh, while the additional element 9 of the comparison generates a signal (fig. 2UK), arrives at the second input of the element b, the third input of which receives pulses from the oscillator.7 of a stable high frequency.

At the moment of coincidence of the signals at the three inputs, the element Ib opens and the pulse d of the generator 7 (Fig. 2-3) passes as the pulse of the end of the time interval. The same impulse comes through an additional element AND NOT

11 to the reset input of the counter 3 and to the zero setting input of the trigger 12. The pulse counter 3 is set to the zero state, the key 1 is closed, the trigger 12 is set to the zero state (Fig. 2a). The subtractive control input of the reversible counter 8 and the first input of element And 6 are supplied with a low potential outputted by the comparison element 5. The device returns to its original state.

The proposed binary-to-time converter will reduce the pulse frequency of the reference frequency generator, while maintaining high conversion accuracy, and therefore reduce the number of bits of the pulse counter, the number of inputs.

Claims (2)

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