SU1280703A1 - Converter of serial variable-length code to parallel code - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in digital data exchange systems: communication lines to convert a serial variable length code into a parallel one. The aim of the invention is to expand the field of application of the converter due to the possibility of receiving code messages of various lengths and its functionality by controlling the received information. The goal is achieved by introducing the second shift register, the decoder, the first and second groups of AND elements, the OR elements, the EXCLUSIVE OR element, the NOT element, the AND elements, the second trigger n: the first shift register is entered (n + 2) th bit. The possibility of receiving code dressings of various lengths is ensured by the fact that the initial part of the received code code, containing the format code, is received in the second shift register and controls the decoder connecting to the mode trigger one of the bits of the first shift; Simultaneously, the control of the received parity information is carried out, 1 Il.

Description

one

The invention relates to automation and computer technology and can be used in digital data communication systems for converting a serial variable-length code into a parallel one.

The purpose of the invention is to expand the field of application of the converter due to the possibility of receiving code dressings of various lengths and its functionality due to the control of the received information.

The drawing shows a structural diagram of the proposed converter.

Variable length to parallel serial code converter contains (+1) bit size shift register 1, element 2, element

12807032.

Pa 6. The same signal, inverting on the element NO 3, prohibits the passage of clock pulses to the clock input of register 1, thus preserving in it the format code of the received code parcel. This code is sent to the decoder 5, which in accordance with it opens one AND element from each group 13, 14, allowing receipt of the trigger 4 on the clock input through the OR 1 element 1 of one of the bits of register 6, and also allows passage to the input an EXCLUSIVE OR 10 element through the OR element 1I of the previous register bit 6. Regarding the clock pulses received through the AND 7 element on the register 6, the incoming parcel is recorded at 10

J5

NOT 3, first trigger 4.mode, decrypted- 20 than the control is accepted first

rator 5 received word length, (n + 2) -display shift register 6 element AND 7, second trigger 8, element AND 9, element EXCLUSIVE OR 10 elements OR 11 and 12, first group 13 elements AND, second group 14 elements AND The drawing also denotes a clock input 15, an input 16 The beginning of a message, an output 17 Ready and 18 Reliability and information input 19.

The Converter operates as follows.

The input 16 receives a signal, which records a logical 1 in the first bits of registers 1 and 6, zeroing the remaining bits. Simultaneously, this signal arrives at the installation. trigger inputs 4 and 8, set the first to the logical 1 state, and the second to the logical 0 state. In this case, the trigger 4 permits the passage of clock pulses from input 15 accompanying the information bits, through the AND 2 element to the clock input of the register 1, to the The sixth input. Which receives the serial bit code of the format of the received code dressing. The accumulation of information in the register G continues until the logical 1, recorded in the lower order by the signal, the start of the message, will not advance to the (+1) -th discharge. The output from the (+1) -th digit goes to the element And 7, allowing the passage of clock pulses from the input 15 to the element And 9 and the clock input of the register.

2807032.

Pa 6. The same signal, inverting on the element NO 3, prohibits the passage of clock pulses to the clock input of register 1, thus preserving in it the code of the format of the received code parcel. This code goes to the decoder 5, which in accordance with it opens one AND element from each group 13, 14, allowing receipt of the trigger input 4 through the OR element 12 of one of the bits of register 6, and also allows the element to pass to the input EXCLUSIVE OR 10 through the element OR 1I of the previous bit of register 6. According to the sync pulses received through the element AND 7 to the register 6, the incoming code parcel is recorded, at 10

J5

- 20 than the first control is taken

parity bit. At the same time, the clock pulses accompanying the bits of the logic 1, are allocated with the AND 9 element, arrive at the input of the counting trigger 8 and switch it to the opposite state each time. The reception of information in the shift register 6 is made as long as the logical 1 is written in

the lower order bit on the signal The start of the message will not advance to the bit connected to the open element AND of the second group 14 and determined by the format code of the received code parcel. The signal of this logical 1, having passed through the open element of group 14 and through the element OR 12, arrives at the clock input of trigger 4 and sets it to

logical O. Simultaneously, the counter bit parity from the previous bit of register 6, passed through the open element I of group 13, is compared on the element EXCLUSIVE ШШ 10 with the state of trigger 8, and in case of coincidence of these signals at output 18 of the converter, signal O, which signals the reliability of the received information.

As a result of the transition of the trigger 4 to the state of the logical O at the output 17 of the converter, the logic 1 turns on

the end of the reception of the code message, while the signal from the direct output of the trigger 4 blocks the arrival of clock pulses through the elements 7 and 2 to registers 1 and 6, which leads to the preservation of the received information until the next pulse.

Claims (1)

The invention relates to automation and computer technology and can be used in digital data communication systems for converting a serial variable-length code into a parallel one. The purpose of the invention is to expand the field of application of the converter due to the possibility of receiving code dressings of various lengths and its functionality due to the control of the received information. The drawing shows a structural diagram of the proposed converter. A sequential variable-to-parallel code converter contains (+1) bit size shift register 1, AND 2 element, NOT 3 element, first 4. mode trigger, decoder 5 received word length, +2) - bit shift register 6 element AND 7, second trigger 8, element AND 9, element EXCLUSIVE OR 10 elements OR 11 and 12, first group 13 elements AND, second group 14 elements I. The drawing also indicates the clock input 15, input 16 Start of message, outputs 17 Ready and 18 ostovernost and an information input 19. The converter operates as follows. The input 16 receives a signal, which records a logical 1 in the first bits of registers 1 and 6, zeroing the remaining bits. At the same time, this signal is sent to the installer. trigger inputs 4 and 8, set the first to the logical 1 state, and the second to the logical 0 state. In this case, the trigger 4 permits the passage of clock pulses from input 15 accompanying the information bits through the AND 2 element to the clock input of the register 1, to information input. Which receives the serial bit code of the format of the received code dressing. The accumulation of information in the register G continues until the logical 1, recorded in the lower order by the signal, the beginning of the message, will not advance to the (+1) -th discharge. The output signal from the (+1) -th discharge arrives on the element And 7, allowing the passage of clock pulses from the input 15 to the element And 9 and the clock input register12 32. Pa 6. The same signal, inverting on the element NO 3, prohibits the passage of clock pulses to the clock input of register 1, thus preserving in it the code of the format of the received code parcel. This code goes to the decoder 5, which in accordance with it opens one AND element from each group 13, 14, allowing receipt of the trigger input 4 through the OR element 12 of one of the bits of register 6, and also allows the element to pass to the input EXCLUSIVE OR 10 through the element OR 1I of the previous bit of register 6. For sync pulses coming through the element AND 7 to register 6, the incoming code message is recorded, with the parity check bit being received first. At the same time, the clock pulses accompanying the bits of the logic 1, are allocated with the AND 9 element, arrive at the input of the counting trigger 8 and switch it to the opposite state each time. Receipt of information in the shift register 6 is made until logical 1, recorded in the lower bit of the signal, the message start, will not advance in the bit connected to the open element AND of the second group 14 and determined by the format code of the received code package. The signal of this logical 1, passed through an open element of group 14 and through an element OR 12, arrives at the clock input of trigger 4 and sets it to the state of logical O. At the same time, the counterpart parity from the previous register bit 6, passed through an open element And the group 13 is compared on the EXCLUSIVE SHSh 10 element with the state of the trigger 8, and in case of the coincidence of these signals at the output 18 of the converter, the signal O appears, which signals the reliability of the received information. As a result of the transition of the trigger 4 to the state of logical O at the output 17 of the converter, logical 1 is signaled to the end of reception of the code message, while the signal from the direct output of trigger 4 blocks the arrival of the clock pulses through the And 7 and 2 elements to the registers 1 and 6 which leads to saving the received information until the next pulse. Start of message. Claims: Variable-length serial code converter to parallel containing the first (n + 1) discharge shift register, where n is the length of the received code signal, the first trigger, whose installation input is combined with the installation input of the first shift register and is the beginning of the converter's input, characterized in that, in order to expand the area of its reception due to the possibility of receiving code messages of various lengths and expanding its functionality by controlling the received information, the second (+1) -shift shift register is entered into the converter, where E is the length of the code of the format of the received code parcel decoder, the first and second groups of AND elements, OR elements, the EXCLUSIVE OR element, and AND elements, the first shift register is entered (n + 2) -th bit, the information input of the first shift register is combined with the information input of the second shift register and the first input of the first element AND, and is the information input of the converter, the outputs of the first E bits of the second shift the register is connected to the corresponding inputs of the decoder, the outputs of which are connected to the combined first: the inputs of the respective elements of the first and second groups, the second inputs of the corresponding elements of the first and second groups are connected to the outputs of any two adjacent bits of the first shift-register, the outputs of the elements And the first group is connected to the corresponding inputs of the first element OR, the output of which is connected to the first input of the element EXCLUSIVE OR, the elevations of the elements AND of the second group are connected to the corresponding and the inputs of the second element OR, the output jcoTOporo is connected to the clock input of the first trigger, the inverse output of which is the output of Ready Transformer, the direct output of the first trigger is connected to the combined first inputs of the second and third elements AND, the second inputs of which are combined and are clock the device input, the output (1 + 1) of the second shift register is connected to the third input of the second element AND directly and to the third input of the third element AND through the NO element, the output of the third element And is connected to the clock the output of the second shift register; the output of the second element I is connected to the clock input of the first shift register and the second input of the first element I, the output of which is connected to the clock input of the second trigger, whose installation input is combined with the input of the second shift register and connected to the input of the beginning of the converter message , the inverse output of the second flip-flop is connected to the second input of the EXCLUSIVE OR element, the output of which is the output Reliability of the converter.