SU1280550A1 - Digital-analog tachometer - Google Patents

Abstract

The invention relates to a measurement technique and can be used to precisely measure and record the angular velocity of rotation of a shaft. The purpose of the invention is to simplify the tachometer. In Counter 5, a digital code is formed that is proportional to the period following the pulses of sensor 2. The shaper 4 is triggered on the leading edge of these pulses, the Overwrite command from which through the OR 13 circuit goes to the corresponding

Description

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input of register 7, and signal code 5 is overwritten in register. From the outputs of Reset generator 4, a pulse arrives, which sets the counters 5 and 6 to the initial state. In the intervals between the Reset commands, the counter 5 through the circuit AND 9 is filled with the pulses of the generator 1 reference frequencies.

If the number N of the digits of the code rewritten from counter 5 to register 7 does not exceed the number M of the mantissa of the digital-to-analog converter 3, this code is converted into an analog voltage proportional to the measured speed. 1 il.

The invention relates to a measurement technique and can be used to precisely measure and record the angular velocity of rotation of a shaft. The purpose of the invention is to simplify the tachometer. The drawing shows a functional diagram of the device. The digital-analogue tachometer contains the generator I reference frequency, sensor 2, digital-analogue converter 3 shaper 4 pulses of rewriting and reset, the first 5 and second 6 counters universal shift register 7, delay element 8, first 9, second 10, and third 11 schemes I, first 12 and sec 13 schemes OR. The output of the generator 1 of the reference frequency is connected to the first inputs of the first 9 and second 10 J circuits I. The output of the sensor 2 is connected to the input of the driver 4 rewriting and reset pulses, the outputs of which are connected to the corresponding inputs of the First 5 and second 6 counters, and the output Overwriting - with the first input of the second circuit OR 13, the second input of which is connected to the output of the second circuit AND 10. The output of the first circuit AND 9 is connected to the counting input of the first counter 5, the information outputs of which are connected to the information inputs of the parallel recording station wagon Nogo register 7 and the overflow output - to the input of the delay element 8. The information outputs of the low bits of the universal register 7 and the outputs of the second counter 6 are connected to the inputs of the Mantissa and the Order of the digital-to-analog converter 3, respectively. The output of the delay element is connected to the second input of the first AND 9 circuit, the information input of the sequential recording of the universal register 7 and the first move of the first OR circuit 12, the remaining inputs of which are connected to the corresponding information outputs of the higher bits of the universal register 7, and the output to the second the input of the second circuit AND 10 and the input Control of the recording mode of the universal register 7. The output of the second circuit OR I3 is connected to the input Record of the universal register 7 and the counting input of the second counter 6, information outputs cat Through the third circuit, And 11 is connected to the Inhibit input of this counter. The device works as follows. The sensor 2, having, for example, a magnetic coupling with the shaft, generates a sequence of pulses with a repetition period multiple to the rotation period of the shaft. Counter 5 generates a digital code proportional to the period of the pulse of sensor 2. "On the leading edge of these pulses, the driver 4 is triggered. The Overwrite command of the driver 4 through the OR circuit 13 arrives at the corresponding register 7 input. the outputs Reset the imager 4 receives a pulse, which sets the counters 5 and 6 to the zero initial state. In the intervals between the Reset commands, the counter 5 through the AND circuit is filled with the pulses of the generator I of the reference frequency.

If the number N of the significant bits Kojja, rewritten from counter 5 to register 7, does not exceed the number M of the digits of the digital-to-analog converter 3, this code is directly converted to analog voltage inversely proportional to the law. Thus, the output voltage of the converter 3 is proportional to the measured speed. : In cases when N M, single signals are present in the higher bits of register 7, this leads to the appearance of a high potential level at the output of the OR circuit 12, switching the register 7 to the sequential information recording mode and simultaneously generating a synchronization pulse with the output frequency generator signal I reference frequency, With the arrival of each synchronization pulse, the contents of register 7 shift to the left. In this case, the information of the least significant bit is lost, and a zero code is entered in the most significant bit. The shift of information in the register is carried out until all the inputs of the OR 12 circuit have zero levels. The number of shifts n, corresponding to the order of the measurement result, is counted by the second counter 6. I

The shift of the contents of register 7 by n bits must correspond to a decrease in the output voltage of the device by a factor of 2. Such a reduction is achieved by controlling the transducer 3 on the input port.

E. If the shaft is stationary, the first counter overflows 5. The output of this counter overflows is set to a single level. This leads to blocking of the counting pulses through the first AND 9 circuit and the appearance of a signal at the information input of the sequential recording of the register 7. At the same time this signal through the OR circuit 12. translates case

7v sequential information recording. With the release of the second scheme And

10 and the second circuit OR 13 to the input of the synchronization register 7 continuously. reference frequency pulses arrive

As a result, the number III. In.I corresponding to the minimum output voltage of the device is recorded in register 7. Simultaneously, the synchronization pulses are counted by the second counter.

6. After the second counter 6 reaches state III.I, the third AND II circuit is triggered and the synchronization pulses stop. To the unit levels of all significant bits and mantissa of the measurement result, respectively

This is a zero output level.

signal device. , At low speeds of shaft rotation

those. while appearing

the binary counter 5 reset signal and the Overflow signal, it is necessary to ensure a zero output level of the device. This is achieved by introducing a delay element 8 that prevents register .7 from switching from serial to parallel during reset of the binary counter 5.

Claims (1)

Invention Formula A digital-analogue tachometer containing a reference frequency generator, a digital-to-analog converter, a sensor, a first AND circuit, two counters, a shaper of rewriting and resetting chips, the input of which is connected to the output of the sensor, and the outputs Reset to the corresponding counter inputs that in order to simplify it introduced a universal register, second and third circuits AND, the first and second circuits OR.and a delay element, with the output of the reference frequency generator connected to the first inputs of the first and second circuits AND, output Overwriting the forms the overwrite and reset pulsator - with the first input of the second OR circuit, the second input of which is connected to the output of the second AND circuit, the output of the first AND circuit is connected to the counting input of the first counter, whose information outputs are connected to the information inputs of the parallel register of the universal register, and the Overflow output - with the input of the delay element, the information outputs of the lower bits of the universal register and the outputs of the second counter are connected to the inputs of the Mantissa and the Order of the digital-to-analog converter. , the output of the delay element is connected to the second input of the first AND circuit, the information input of the serial record of the universal register and the first input of the first OR circuit, the remaining inputs of which are connected, 1280550. jo Records with the corresponding information connectors with the input Record by the universal outputs of the senior bits of the universal register and the counting input of the secondary register, and the output from the second counter, the information outputs the input of the second scheme And and the input of the Manager — which through the third scheme register, the output of the second scheme OR co-counter.