SU1277146A1 - Logarithmic analog-to-digital converter - Google Patents

Abstract

The invention relates to automation and computing and can be used, in particular, in information and measurement and control systems for obtaining the digital value of the input voltage logarithm. The aim of the invention is to expand the scope. The converter operates iteratively (cyclically), and each iteration always consists of two cycles, b depending on the switching program of two-position switches, written in the memory register of the syncrod block, the converter can operate in nine different modes. 1 hp f-ly, 1 ill. (L

Description

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O5 The invention relates to automation and computer technology and can be used, in particular, in information metering and control systems for obtaining a digital value of the input voltage logarithm. The purpose of the invention is the expansion of the field of application. The drawing shows a block diagram of a logarithmic analog-to-digital converter. The converter contains switches 1–4, the driver 5 exhibits and a pre-charge 6 diode, two May staff resistors 7 and 8, operational amplifier 9, scaling amplifier 10, integrator 1 1, analog bootloader 12, voltage-frequency converter 13 ( FNT), key 14, counter 15, memory register 16, digital-to-digital converter 17 (D / A converter), synchronization unit 18 and driver 19 pulses. The synchronization unit 18 contains a memory register 20, a trigger 21, elements 22 and 23 of an I-N-W-NOT, differentiating chain 24. The operation of the converter occurs iteratively, ionically (cyclically), with each iteration always consisting of two cycles. Depending on the rule of the switches 2 and 3, the device operates in any of the nine nine relays (the switch program of the switches 2 and 3 is written to the register 20 of the synchronization unit 18, trigger 21 - the trigger trigger). The considered 9 modes are divided into 3 groups, 3 in each. Group A logarithmic mode 1 1. In this group of modes, the device provides a measurement (in a logarithmic scale) of averages, exponential, with averages and logics of averages for constant and variable signals of an arbitrary form. Consider the first mode of the P1-STOCK devices, the counter 15 is reset to zero (the reset is then automatically performed), the initial approximation code is recorded in register 16. The first cycle is switches 1 and 4 in the upper position, switches 2 and 3, respectively, in the upper and down positions (this position ne-i of the switches 1-4 is shown on the same side). With this position of switches 2 and 3, the operational amplifier (together with the driver 5, the exponents and the resistor 8) becomes a potential decisive amplifier, exponentially increasing the input voltage. The integration (on the read input of block 11) of the voltage Zjj from the output of the DAC 17 is performed during the time interval Tx - id + oL) k J e -dt + p, where X is the initial voltage of the integrator; z is the output voltage of the DAC 17h, equal to the code being converted at the input of the DAC; f is the transmission coefficient of the scale amplifier 10; k - transfer coefficient integrator 1 11; oL and A are respectively multiplicative and additive inaccuracies, Analogue Auxiliary Element 12 is in storage mode (old value), LFM 13 pulses through open 1SHOOP 14 during the entire first clock cycle arrive at counter 15, forming a code. E, This is where the first beat ends. The second cycle - switches 1 and 4 are shifted to the lowest position; switches 2 and 3 are also in the lower position. With such a position of the switches 2 and 3, the operational amplifier 9 becomes the usual large-scale amplification, the transmission coefficient of which is equal to the ratio of the resistances of the resistors 8 and 7 (in our case, the indicated coefficient is 1, since Rg is R). The integration is performed (by s; the first input of the integrator 11) of the measured input signal x (t.) During the same time interval T. - (1 + ol) k x (t) dt, (1) o. where X, is the new improved approximation at the integrator output. Similar storage element 12 is open — during the entire second cycle, the output voltage of the integrator 11 is continuously recorded in the analog storage element 12. This completes one iteration. Upon its completion, at the output of the FNC 13, we obtain a new, refined value of the frequency f |. The second iteration is completely analogous to the first one. First cycle — switches 1 and 4 are moved to the upper position, switches 2 and J, respectively, in the upper and lower positions. Code 2, from counter 15, is copied to register 16, after which the impulse of the differentiating chain 24, counter 15, is reset to zero. . Voltage 2 is integrated from the output of the DAC 17 during the interval T X, - (- (II h dt p), where X jj is the voltage at the integrator output, obtained after the first iteration. PNC pulses 13 through the public key 14 during the entire first one goes to counter 15 to form a new code 2 2. The second cycle - switches 1 and 4 are moved to the lower position, switches 2 and 3 are also in the lower position. The measured input signal x (t) is integrated into current of the same time interval T T x, X, (l + ot) k I e - dt + pi t + y (1 + s) k, x (t) dt + pi t x2 X + dk I e .dt - (1 + ci ) k I x (t) dt} ° (2) where x is a new, improved approximation at the integrator 1 1 output. Analog storage element 12 is open — throughout the second clock cycle, the voltage from the output of integrator 11 is continuously recorded in the analog storage element 12. At the output of the FNM 13, a new, refined value of the frequency f arrives. At this, the second iteration is completed. All subsequent iterations are carried out in the same way as described. As a result, through n iterations, as follows from (1) and (2), we get .., n; V {(1-) h | dt - (1 + Ы) k I x (t) dfj. (3). Where X is the output voltage of the integrator 11 at the nth iteration; Z is the code written in the register. With an increase in the number of iterations of the magnitude of their X., the P 1 is closer and closer to its established value of X. In the limit, in steady state, the output value of integrator 11 does not change from iteration to iteration those. x x X. As follows from algorithm (3), the expression in braces is zero ,, I z. . j, j ,, t dt О Where Z is the code in register 16 in steady state. From (4) it follows} Z, r I e dt x (t) dt, (5) ° i. in the steady-state mode, the negative increments of the output value of the integrator 11 in the first cycle are equal to the positive increments in the second cycle. In this case, as follows from (5), the additive and multiplicative errors of the blocks are corrected and are not included in the final result. Carrying out the sign of the integral in (5) and uchitsha that G dt T, we finally get about T z 1n {- I x (t) dt). (7) Thus, in steady state, the output value of the entire device is equal to the integral average value on a logarithmic scale. For constant input values x from (7), we have z Inx, which corresponds to the mode of the prototype device. On this, the analysis and description of the first mode of operation is completed. Consider the second device mode. Measurement of exponential means on a logarithmic scale. In the initial state, the counter 15 is reset to zero, and in register 16 the initial approximation code z, the Switches 2 and 3, which set the operating mode of the entire device, are set for the entire operation, respectively, to the upper and lower positions. at the same time, each iteration, as before, consists of two cycles. The first cycle - pereyaschiateli 1 and 4 again in the upper position. The voltage ZQ is integrated from the output of the DAC 17 during the time interval T e ° dt + / c Xp hf1 + S) k Analog storage element 12 is in the storage mode of the old value. Patch pulses 13 through the public key 14 (during the entire first clock cycle) enter counter 15, forming a new code z /.,. The second cycle - switches 1 and 4 are moved to the lower position. The integration is performed (by the summing input of block i 1) of the measured input signal during the same time interval T x. | X - v | (1-i-cL) k I dt T; tt) o - (1 + oL) k e dt (7 is a new, improved approximation at the output of the integrator 11. Analog memory element 12 is open - output voltage The integrator 11 is continuously rewritten to block 12. By the end of the second clock. (and one iteration as a whole), at the output of the PAC 13, we obtain a new, refined frequency value. The second iteration is completely analogous to the first. First clock - translators 1 and 4 in the upper position The code z, from counter 15 is copied to register 16, after which the pulse of the differential chain 24 counter 15 is reset in n Voltage z is taken from the output of the AP 17 during the time interval T (1 + s) k e dt + p1 dt o The PNC pulses 13 through the key 14 enter the counter 15, forming a new second cycle - switches 1 and 4 The input signal is integrated during the time interval T. (1 + oi) kjfx (t) -.0 - d + of) k ,, I dt) Analog storage element 12 is open - integrator output voltage 1 1 during the entire second clock cycle are continuously recorded in block 12. At the output of the PLF 13, we obtain a new refined value of the frequency f g. volume second iteration is complete. Wire all subsequent; e iteration is similar to the described (7) and (8), we obtain for the n-th iteration e dt ..-, -t (x (t) - (l + d.) K, With the increase in the number of iterations x. In the steady-state mode, the output value of the integrator 11 does not change from iteration to iteration: xx x. As follows from (9), this means that the expressions in brackets in (9) T. dt - (1 + s) kJe (1 + o1) k, dt O From xCt) e. dt (z) - code in register 16 in steady state). Carrying out in (11) e for the sign of the integral and taking into account that, dt T, we finally get °. G 1 I - {-T

Thus, in the steady state, the output value of the entire device, TBa, is equal to the exponential average value of x (t) on a logarithmic scale. In this case, as follows from (10), (11) (12), the additive and multiplicative errors of the blocks are excluded and are not included in the final result.

The third mode. Measurement of logarithmic means on a logarithmic scale.

Again in the initial state, the counter 15 is reset to zero, and the initial approximation code Zg is recorded in register 16.

Switches 2 and 3, which determine the operation of the entire device, are in the upper and lower positions at the first step of each iteration, and at the second step of each iteration, their position is reversed.

The first cycle - switches 1 and 4 in the upper position. Switches 2 and 3 are respectively in the upper and lower positions.

Voltage Z is integrated from the D / A output 17 during the time interval T

t

x (1 + ol) -k I e dt + (B1., o

The impulses of the PNC 13 through the key 14 enter the counter 15, forming a new code Z /.

The second cycle - switches 1 and 4 in the lower position, switches 2 and 3, respectively, in the lower and upper. Due to this position of switches 2 and 3, the operational amplifier 9 is transformed into an oarithmic amplifier.

The integration (on the summing input of the block 11) of the measured input signal x (t) is performed during the interval T

T x (1 + d) k j e dt + (3 +

+ l.V (+} k f In x (t) dt + pi;

0 T x d + ol) k f e dt t b - (1 + oL) k J In x (t) dt} (13)

about

during the entire second cycle, the output voltage of the block 11 is copied to the analog storage element 12. At the output of the LPF 13, we obtain a new, refined value of the frequency f. .

In this, the first iteration is completed, the second iteration is carried out similarly to the first, with the result that

as follows from (13), we obtain

T

X X, -Y | (I + OL) kj e dt 4 o

- (1 + oL) k In x (t) dt} (14)

0

Having carried out all the subsequent iterations 1 described similarly, we get dn pth. Iteration

,,, x, -r {(I-S) kj dt t o

- (1 + dl) k J In x (t) dtj (15)

1D.

In the steady state x x x, a, the expression in curly brackets in. (15) is zero

(1 + сО k Г е dt - (l + oC) k ,, S о о «In x (t) dt 0 (16)

From (16) follows

| e dt f In x (t) -dt. (17)

about . o From here, finally, we get

z In l-fl dtj. (18)

Thus, in this third mode of operation, the output value of the entire device is equal to the logarithmic average value x (t) on a logarithmic scale. Moreover, as follows from (16), (17) and (18), the additive and multiplicative errors of the blocks are corrected again and do not affect the final result.

Group B - antilog regimes.

Claims (1)

In this mode, the device provides a measurement of average, exponential averages and logarithmic means of constant and variable signals of arbitrary shape. The results obtained are presented in the anti-log (exponential) scale. The fourth mode of the device. Measuring averages on an anti-log scale. The initial state of counter 15 and register 16 is the same as in the previous modes. Switches 2 and 3, which set the operating mode of the entire device, are set in the first cycle each, the iterations to the lower and upper position (respectively), and in the second cycle of each iteration, both switches are in the lower position 1-sh :. Consider immediately the nth iteration (all previous iterations are similar.) The first cycle - switches 1 and 4 in the upper position, switches 2 and 3, respectively, in the lower and upper positions. Operational amplifier 9 become with a logarithmic amplifier. The voltage is integrated from the output of the DAC 17X. (Hd) k In z dt + p. PMP pulses 13 through open key 14 enter counter 15, forming a new code z, | . The second cycle - switches 1 and 4 in the lower position, switches 2 and-3, too, in the lower polarization. Operational amplifier 9 operates as a large-scale amplifier (repeater). The input signal x (t) is integrated (by the summing input of the block 11) -lY (1 + oL) k In Z dt -Hp h + 1 h - and jn T ° (1 + d.) Kx (t) dt 4 t "Nr - 1 1 - (l + ol) k, | x (t) dt} ° (19) The resulting algorithm describes the operation of the device at all iterations n 0,1,2, ..,. In the case of the FNP 13 We receive a new frequency value. As n grows, the output value of the integrator 11 tends to set the schemus to x. In the established with the mode x x, x at the same time, as follows from (19), the expression in curly brackets in (19) is zero (1 + о () k,) In z dt - (1 + di) k ,,: n «x (t) dt 0. From- (20) we get In In z dt x (t) dt now, taking In z by the integral sign and taking into account that f dt T, we finally have f jf. I J z e T. antilnj --- x (t) dtj. (22) Expression (22) shows that the output value of the device in this mode of operation is equal to the integral average value x (t) in the anti-log scale. As follows from (20), (21) and (22), the additive and multiplicative errors of the blocks, as before, are corrected and are not part of the final result. Fifth device mode. Measurement of exponential averages on an anti-log scale. Initial state - counter 15 is reset to zero, in register 16 the code of initial approximation z is written. Switches 2 and 3, which set the mode of operation of the entire device, are set up in the first cycle by iteration into the lower and upper position (respectively), and in the second cycle they change their position to the opposite. Consider the nth nterail. The first cycle - switches 1 and 4 in the upper position, switches 2 and 3, respectively, in the lower and upper. The operaddone amplifier 9 operates in a logarithmic amplifier mode. We are integrated with the output of the D / A converter 17 of the z Tx, (1 + Yu In z dt + PNC 13 pulses are fed to the counter 15, forming a new code z. The second cycle - switches 1 and in the lower position, switches 2 and 3, respectively, in the upper and lower. Operational amplifier 9 operates in the mode of an exponential decisive amplifier. 111277146 The input signal x (t) n „is integrated into the current (v., J., alj. y-rv (1 + fj) k Iri z dt + PJ + 1, h .; K j and T xtt) + 1U d + d; kj e dt + pj. 9 P XX -f {(1 + c () k In. X I) (23) O The algorithm (23) describes the operation of the device on all iterations n O, 1, o y Ha output of the FNP 1 3, the new value of frequency f. With an increase in the number of iterations n, the output value of block 11 tends to the steady-state value X. In the limit x x x, and from (23) we have T (1 + d) k In z dt 0 ,, 4, - ( 1 + dl) k, I e O. o From this it follows that mxx (i) 1 e .dt. (24) In z dt now, the carry-out of In z 33 is the integral sign, finally we get. 2 sx (t), t g 1 g x (t) -) antiln -f- je dtj. (25) о Thus, the code z in register 16 is equal to the exponential average value of x (t) in the anti-log scale. In this case, the errors of the blocks, as before, are corrected. Sixth mode. Measurement of the logarithmic means on the anti-log scale. The initial state of all blocks is the same as in other modes. Switches 2 and 3, which set the device operation mode for the entire duration of operation, are set to the lower and upper positions, respectively. Operational amplifier 9 operates in a logarithmic amplifier mode. Consider the nth iteration. The first cycle - switches 1 and 4 in the upper position. . The voltage Zr is integrated, from the output of the GAL 17 12 tg (1 + dl) k In z dt + P. and Impulses GTNC 13 arrive in the counter impulses IPC IJ nUCTyj. -, 7 image z, code. The second cycle - switches 1 and d jg lower position. The input signal x (t) t -.- is integrated. -I 1 1 P (1 + d) k f In x (t) + pl; J t yf (+ () jf In z dt JI rt (+) j Y y. Jj (26) J The resulting algorithm records the operation of the device for all, 1,2, ...., with increasing number of iterations, the device tends to steady In the limit x ,, x, x, as follows from (26), the expression in curly brackets is zero t (l + rt) kf dt оT - (l + ot) k (In x (t) dt 0 i From here f t. | In z dt In x (t) dt i В Re-taking In z for the integral sign, get la, get EbUt) dt ze Z e antiln | - - | In x (t) dt, (27) This corresponds to the logarithmic average value in the anti-log scale. Note that expression (27) is an analogue of the geometric mean j uj signals) t Chlx X xj e e vx ,, x,. ... x As in the considered modes, the adjective and multiplicative errors of the blocks are corrected and are not included in the final result (27). Group B - linear modes. In this group of modes, the device provides a measurement of average, 13 exponential averages and logarithmic averages of constant and variable signals of arbitrary shape. At the same time, the obtained results are presented in the usual (linear) scale. Seventh mode. Measurement of average values in a linear scale. Initial state as in other regs. Switches 2 and 3 at all iterations in the lowest position. Operational amplifier 9 works as a repeater. Consider the nth iteration. The first clock cycle is switches 1 and 4 in the upper position. Integration by subtracting the input to the input of the block 11 z dt + (bl. X - (1 + pL) k, the impulses of the IFF 13 arrive in the counter 15, forming a new code z, .. The second clock is the switches 1 4 in the lower position. Integration x ( t) on the summing input of the block 11 T x x, –y (1 - “- c) k. Z dt h +) 1 I– and J n - (1 + Ы) k, Jx (t) dt} ° ( 28 о With an increase in the number of iterations x - h and + 1 In the steady redema, as with blowing from (28), we have m. (1 + s) k 2 dt. - (1 + d) kfx (t) dt O, From here after obvious transformations we get, - 1 x (t) dt 2 - -5 Expression (29) defines the known integral average, which is analogous to the arithmetic mean for continuous For the measured measured values of x (t) X const, the considered value gives Z, i.e., the standard analog-to-square conversion of the vanes in the linear scale. At the same time, the errors of the blocks are corrected again and do not enter: (29). 6 Eighth mode. Measurement of the exponential centerpiece in a linear scale. The initial state is unchanged. Switches 2 and 3 are set in the first iteration stage of the iteration both lower half, in the second cycle, respectively, in the upper and lower positions, Consider the nth iteration. The first cycle - switches 1 and in the top position. Integration by the subtractive course of the integrator 11 T X (l + d) k ,, z dt + B1, h J The pulses 13, entering the counter 15, form a new code z. Second Pulse - switches 1 and 4 in the lower position. Owing to switch 2 and 3, Operational amplifier 9 operates in the exponential solver mode. Integration over integrator input 11 (1 + ci) k ,. n.1 h - (1 + d) k J e With the increase in the number, the iterative device tends to become an I I c mode in which x x, j K, which, as follows from (30), means T (1 + oi) k J z dt ° p (t) - (1 + ci) k. dt oh From here, reducing (1 -: - s) k and taking r out of the integral sign, we finally get Expression (31) and is the desired exponential average value of the signal x (t). Ninth mode. Measurement of logarithmic means in the extremity scale. The initial state is without change. Switches 2 and 3 are set at the first cycle of each iteration, both in the lower position and in the second, respectively, in the lower and upper. Consider the nth iteration. 15 First tact - switches 1 and 4 in the upper position. Integration over the subtracting input of the integrator 11 - (1 +) k. f z, dt hr, the PNC pulses 13 form in the counter 15 a new code z. The second cycle - switches 1 and 4 in the lower position. Operational amplifier 9 due to switches 2 and 3 is transferred to the mode of exponential amplifier. Integration over the summing input of the block .11 .., n (But) k g dt t J - (1 + d) k J In x (t) dt j. (31) From (31) for a steady state operation of the device, we obtain m. (1. + d) k z z dt - (1 + Ы) k I In x (t) dt 0. Отс From here, after obvious simplifications, we finally get t Z −1 − f In x (t) dt, (32) Note that the additive and multiplicative errors of the blocks are corrected and have no effect on the final result. Thus, as follows from the description of the operating modes, the device provides measurement of nine different integral characteristics of fixed and variable signals of arbitrary shape, including the average (integral exponential average and logarithmic average of the input measured signals. At that, the measurement result be represented in any of the three (optional) scales — linear, logarithmic and anti-logarithmic. Claim 1. Logarithmic analog-to-digital conversion Is it a first-order switch, a first-signal input to the information input 146 of the converter, and an output to the forefinder exponent of the exponent, an analog storage element whose output is through a series-connected voltage-frequency converter and a key connected to the counter input of the counter the output of which is connected to the information input of the memory register connected by the code to the input of the digital-to-analog converter, the pulse driver, the input of which is connected to the supply voltage bus network, and the output - with the clock input of the synchronization unit, the first output of which is connected to the control input of the key and the control input of the analog storage element, is distinguished by the fact that, in order to expand the field of application, logarithmized are entered into it: ir1 diode, two large-scale resistors, a second, third and fourth switches, an operative amplifier, a large-scale amplifier and an integrator whose output is connected to the information input of an analog storage element, and the direct and inverse inputs are connected to the corresponding the fourth output switch, the information input of which is connected to the output of a scale amplifier connected to the output of the operational amplifier and the output of the third switch, the signal inputs of which are connected to the cathode of the logarithmic diode and the first output of the second scale resistor, the second output of which is connected to the anode of the logarithm diode and inverting the input of the operational amplifier connected to the output of the second switch j whose signal inputs are connected to the output form a l exponent and the first output of the first large-scale resistor, the second output of which is connected to the output of the first switch, the second signal input of which is connected to the output of the digital-to-analog converter, the non-inverting input of the operational amplifier is connected to the zero potential bus, the first output of the synchronization unit is connected to the control inputs of the first and fourth switches, the control input of the analog storage element and the write resolution of the write register of the memory register, the second, the third and the fourth. synchronization is connected respectively to the input zero the counter, controlling the inputs of the second and third of the switches. 2, The converter according to claim 1, wherein the synchronization unit contains a memory register, two AND-OR-NOT elements and a differentiating chain, the trigger input is connected to the clock input of the unit sync, and the direct output is the first output of the sync block, connected to the first the inputs of the first and second elements I-BL-NOT and through the diff1 |) differentiating chain to the second output of the synchronization unit, the inverse output of the trigger is connected to the second inputs of the first and second elements AND-OR-NOT, the third and fourth inputs of which are connected respectively to the first, the second and third, fourth outputs of the memory register, the outputs of the first and second AND-OR-NOT elements are, respectively, the third and fourth outputs of the sync block.