SU1727130A1 - Device for solving differential equations - Google Patents

Abstract

The invention relates to computing and can be used in the construction of analog-digital integrating machines and specialized processes for solving systems of differential equations. The aim of the invention is to expand the functionality by solving an inhomogeneous system of differential equations with variable coefficients and forming the found solution in the form of a continuous function of time. Achieving a positive effect is based on the continuity properties of parabolic splines and their first derivative, which allows us to obtain a global approximate solution that is defined over the entire time interval. 2 Il.

Description

 The invention relates to computing and can be used in the construction of analog-digital integrating machines and specialized processes designed to solve systems of differential equations.

A device is known for solving differential equations in an implicit alternating direction scheme, containing a matrix of KxL of arithmetic units, a synchronization unit. When the device is in operation, a hardware implementation of an implicit scheme of the Pisman-Ruckford variable flows occurs. The calculation of each iteration is performed in parallel for all values in the corresponding arithmetic blocks of the matrix and reduces to solving a system of algebraic equations with a tridiagonal matrix. This device requires large machine costs, due to the iterative function calculation scheme. In addition, due to the structural constraints imposed by the calculation algorithm, this device cannot determine the fundamental matrix of a linear differential equation.

A device for solving systems of linear differential equations is known, comprising n memory blocks, n shift blocks, n adders, n accumulating adders, control unit, counter, groups of elements U, register, switch, analysis unit, OR element, n encoding elements. The device is designed to solve systems of linear differential equations with constant coefficients X |

Yu

Vsl

with

about

tami species

Y (0) Y0,

where A and B are the matrix and the coefficient vector, respectively.

At each integration step in this device, a first approximation to the solution is found using the interpolation formula and, to satisfy the specified accuracy, the solution is refined using the interpolation formula, with the remainder of rounding used in the next iteration of the calculations using the interpolation formula.

This device requires a lot of machine costs, due to the interpolation calculation scheme, and the increase in the accuracy of the calculations requires even more machine and time costs. Due to the proposed calculation algorithm, this device does not allow solving the system of differential equations with variable parameters and finding the fundamental solution of the system of equations.

The closest in technical essence to the invention is a device for solving systems of differential equations comprising three blocks of permanent memory, three blocks of memory, two multipliers, an adder, and a synchronous generator. This device finds the fundamental solution to a system of equations with variable coefficients.

However, due to the proposed iterative calculation algorithm, this device requires large computational costs. In addition, it does not allow one to solve an inhomogeneous system of equations with variable coefficients and to form the found solution in the form of a continuous function of time.

The purpose of the invention is to expand the functionality by solving an inhomogeneous system of differential equations with variable coefficients and forming the found solution as a continuous function of time.

This goal is achieved in that the device containing the first, second and third blocks of the buffer memory, the first and second multipliers, the first, second and third blocks of memory, the first adder and the sync generator, the first output of the sync generator is connected to the read inputs of the first and second the buffer memory blocks, the initial inputs of the first, second and third blocks of the buffer memory are connected respectively to the first, second and third information inputs of the device, the control input of the clock generator is connected to the input 3 starting the device, the second output of the sync generator is connected to the read / install inputs of the first, second and third memory blocks, the zero input of which is connected to the input of the initial installation of the device,

the initial installation inputs of the first and second memory blocks are connected to the fourth and fifth information inputs of the device, respectively, the output of the first buffer memory block is connected to the first

0 by the information input of the first multiplier, the output of the first adder is connected to the information input of the first memory block, the output of the third block of the buffer memory is connected to the first information

5 input the first adder, additionally introduced a sawtooth generator, quad, the third and fourth multipliers, the first, second and third digital-to-analog converters, the second, third, fourth,

0 fifth and sixth adders, a counter, and

. the output of the first multiplier is connected to the second information input of the first adder, the third information input of which is connected to the output of the second intelligent 5 inhabitant, the first information input of which is connected to the output of the second buffer memory block, and the second information input - with the output of the first memory block and information inputs first

0 digital-to-analog converter and the second memory block, the output of which is connected to the second information input of the first multiplier and information inputs of the second digital-analog converter, and the third memory block whose output is connected to the information input of the third digital-analog converter, is connected to the first digital-analog converter connected to the first input I will give the second third and fourth adders, the outputs of which are connected respectively to the first inputs of the third, fourth multipliers and n of the adder, the output of which is the information output of the device, the output of the second digital-to-analog converter is connected to the second inputs of the second and fourth adders, the third input of which is connected to the third input of the second sum-switch, the second input of the third adder, the first output of the clock generator is connected to the first control inputs of the first and second multipliers, the second control inputs of which are connected to the read output of the third block of the buffer memory, with the third output of the synchronizing generator and with the first control input of the first adder, the second control input of which is connected to the second output of the synchronizing generator, the fourth output of which is connected to. the synchronization input of the sawtooth generator and the counting input of the counter, the initial setup input of which is connected to the input Minus unit of the device, and the output is the first time channel output of the device, the output of the sawtooth voltage generator is connected via a quad to the second input of the third multiplier, the output of which is connected to the second input of the fifth adder, the third input of which is connected to the output of the fourth multiplier, the second input of which is connected to the output of the sawtooth generator and to the first in Odom sixth adder, a second input and whose output is respectively connected to the input device and to the second constant output channel unit time ..

Using a spline approximation to solve a system of differential equations allows us to find a global approximate solution, i.e. solution defined on the whole segment.

The essence of the invention is that, in contrast to the known, in the proposed device, the connections between known blocks are changed, as a result of which the coefficients of the spline are calculated, and additional blocks are introduced, resulting in the formation of a model for solving the system of differential equations in the form of continuous time function.

Fig, 1 shows a structural diagram of the proposed device; in fig. 2 - timing diagrams for the operation of the device.

The device contains the first 1, second 2 and third 3 blocks of the buffer memory, the first 4 and second 5 multipliers, the first 6 adder, the first 7, the second 8, the third 9 blocks of memory, the synchro generator 10, the generator 11 sawtooth voltage, quadrator 12, the first 13, the second 14 and the third 15 digital-analog converters, the second 16, the third 17, the fourth 18, the fifth 2.3 and the sixth 19 adders, the counter 20, the third 21 and the fourth 22 multipliers, the first 24, the second 25, the third 26, the fourth 27 and Fifth 28 information inputs of the device, input 29 of the initial installation of the device, input 30 of the device startup va, 3.1 Minus input unit, the input unit 32 constant, the information output device 33, the first 34 and second 35 outputs channel time. The first 10.1 output of the sync generator 10 is connected to the read inputs of the first 1 and second 2 blocks of the buffer memory. Initial inputs

The settings of the first 1, second 2 and third 3 blocks of the buffer memory are connected respectively to the first 24, second 25 and third 26 information inputs of the device. The control input of the sync generator 10 is connected to the startup input 30 of the device. The second output 10.2 of the synchronous generator 10 is connected to the read inputs of the installation of the first 7, second 8 and third

0 9 memory blocks, the zero input of which is connected to the input 29 of the initial installation of the device. The inputs for the initial installation of the first 7 second 8 memory blocks are connected to the fourth 27th and fifth 28 informational

5 device inputs, respectively. The output of the first 1 block of buffer memory is connected to the first information input of the first multiplier 4. The output of the first adder 6 is connected to the information input of the first 7 memory block. The output of the third block 9 of the buffer memory is connected to the first information input of the first adder 6. The output of the first multiplier 4 is connected to the second information input of the first

5 of the adder 6, the third information input of the second is connected to the output of the second multiplier 5, the first information input of which is connected to the output of the second 2 block of the buffer memory, and the second information input to the output of the first memory block 7 and to the information inputs of the first diffraction converter 13 and the second memory block 8, the output of which is connected to the second information input of the first 4 multiplier and to the information inputs of the second digital-to-analog converter 14 and the third memory block 9, the output of which is connected to information input of the third digital-analog

0 converter 15. The output of the first digital-to-analog converter 13 is connected. to the first inputs of the second 16, third 17 and fourth 18 adders, the outputs of which are connected respectively to the first entrances of the third 21, fourth 22 multipliers and the fifth 23 adders, the output of which is information output 33 of the device. The output of the second digital-to-analog converter 14 is connected to the second

0 inputs of the second 16 and fourth adders 18, the third input of which is connected to the third input of the second adder 16, the second input of the third adder 18 and the outputs of the third digital-to-analog converter 5 15, The first output 10.1 of the synchronous generator 1.0 is connected to the first control inputs of the first 4 and second 5 multipliers, the second control inputs of which are connected to the read input of the third block 3 of the buffer memory, with the third 10.3 output

sync generator 10 and the first control input of the first adder 6, the second control input of which is connected to the second output 10.2 of the synchronization generator 10, the fourth output 10.4 of which is connected to the synchronization input of the sawtooth generator 11 and the counting input of the counter 20, the input of which is connected to the input is 31 minus the unit of the device, and the output is the first 34 time channel output of the device. The output of the sawtooth generator 11 is connected via a quad 12 with a second inlet. the house of the third multiplier 21, the output of which is connected to the second input of the fifth adder 23, the third input of which is connected to the output of the fourth multiplier 22, the second input of which is connected to the output of the sawtooth generator 11 and the first input of the sixth adder 19, the second input and output of which connected, respectively, to the input 32 of the device constants and to the second output 35 of the time channel of the device.

Consider the operation of the device on the example of modeling the process of a system of differential equations

(t) X + Q (t) (X (to) Xa, (1)

where D (t) and Q (t) is the matrix and vector of variable coefficients, respectively.

We use the approximation of the process by a parabolic normalized basis vector spline of dimension n

X (t) V (t), (2)

specified on mesh nodes

A: t-j t-i ....

Aif-i t-i t0 ti .... (3)

elements of which are related by the ratio

 , -1.0, 1.2 .... (4)

V (t) for the interval ti; ti + tj can be represented as

Vi (t) 0.5 fc) 2 V | -1 - 2 V. + B, -i +

+ 0.5 (V) -B

1 + B | + 1 +

i + 6Bi + Bi-H,

+ 0.125E &, - i + 6Bi + Bi-H, (5)

where B | TN; IL & 2, bi3,: ... is the vector of sgbein coefficient, h is the pitch, grids, h tn-i-ti.

For ri wrench, respectively, we get

Јv, (t) () Bl-i-2Bi + B. + l +

,

1 + Bi + i.

Then for the moments of time, 1, 2, ... on the basis of (5) and (6) the solution of the system of equations (1) can be reduced to the form

BM Pf1LiBMH-Pf 1MiBi + Pf1Qi. (7)

where Pi is gb E-hAft), (8)

U –AH (f.), (9)

MRO, 75A (G), No.

E-identity matrix.

The initial conditions for (7) are formed based on the initial conditions of (1). The equations for determining the vectors Bc and B have the form of (1), (2), (5), (6)

B-1-X0- 0, (to) Xo + Q (to),

Bo Xo +: 0, (to) Xo + Q (t0). (11)

The process (1) is modeled by calculating the spline coefficients Bj and using the approximation (2) based on the representation (5) with the initial conditions (11).

In the initial state, the first 1, second 2, and third 3 blocks of the buffer memory from the first 24, second 25, and third 26 information inputs of the device, respectively, recorded the values of the matrices, at times t, 1.2, .... - read by formulas (8), (9), (10) and by given functions of time A (t) and Q (t); The first 7 and second 8 blocks of memory from the fourth 27 and fifth 28 information inputs of the device are written according to the values of the coefficients B and B-1, calculated by formulas (11) for given initial conditions X0 and known functions A (t ) and Q (t) at. The third memory block 9 in the initial state is zeroed by the signal from the input 29 of the initial installation of the device, and the counter 20 records the value -1 from the input 31 Minus one.

The launch of the device is accomplished by starting the synchronization generator 10c of the launch input 30. The clock generator 10, at its four outputs, generates four sequences of clock pulses of the same following frequency (Fig. 2a), which are shifted relative to each other by the delay values determined by the speed of the decision blocks. The first clock pulse from the output 10.1 of the synchronous generator 10 reads the values of the matrices and PO M0, respectively, from the first 1 50 and second 2 blocks of the buffer memory, corresponding to the time point to, and calculates the products P0 in multiplier 4 and Po 1M0Bo in multiplier 5 (Fig. 26 ).

55 The clock pulse from the output 10.3 of the synchronous generator 10 is shifted relative to the clock pulse from the output 10.1 of the synchronous generator 10 by the time required to calculate the matrix products in multipliers 4 and 5 (Fig. 2a, c).

ten

15

20

25

thirty

35

40

45

The first clock pulse from the output 10.3 of the synchronizing generator 10 reads the results of the matrix multiplication operation in multipliers 4 and 5 and the values of the matrix Po Qo corresponding to the time point to from the third block 3 of the buffer memory, and also controls the summation operation in the first adder 6 (Fig. 2c). Thus, the first adder 6 on the first clock pulses from the outputs of 10 L,

10.3 sync generator 10 generates a vector of spline coefficients (7)

., + Po 1MoBo + Po 1Qo.

The clock pulse from the output 10.2 of the synchronous generator 10 is shifted relative to the clock pulse from the output 10.3 of the synchronous generator 10 by the time required to calculate the matrix sums in the adder 6 (Fig. 2a, d).

The first clock pulse from output 10.2 rewrites the spline coefficient vectors: B1 from adder 6 to memory block 7; B0 from memory block 7 to memory block 8; B-1 - from memory block 8 to memory block 9 (FIG. 2 d).

The clock pulse from the output of 10.4 of the synchronous generator 10 is shifted relative to the pulse from the output of 10.2 of the synchronous generator 10 to the time determined by the speed of the blocks 13-18 so that the signals arriving at the inputs of the multipliers 21 and 22 are synchronized with the operation of the sawtooth generator 11 (Fig. 2).

The first clock pulse output 10.4 of the synchronous generator 10 is fed to the counting input of the counter 20 and starts the generator 11 sawtooth voltage (Fig. 2e, g). The sawtooth generator 11 forms at its output a linearly increasing voltage from -U to + U (Fig. 2e) for a period of clock pulses from the output

10.4 clock generator 10 from ti to ti + i. Upon the arrival of the next clock pulse to the sawtooth voltage generator 11, the voltage at the output of the generator 11 abruptly changes from + U to -U and then increases linearly from -U to -HJ over the next period. The moment of crossing the zero level corresponds to the moment ti (Fig. 2e).

Thus, at the output of the sawtooth voltage generator 11, it models 1 - s value t- (t - ti), where h is the grid step, B

In this case, the grid step is chosen uniform, equal to TT and the period of the following clock

one

pulses. Coefficient t- characterizes

the slope of the direct increase of the sawtooth voltage of the generator 11. The signal from the output of the generator 11 is fed to the first input of the sixth 19th adder, the second input of the fourth 22 multiplier and through the quad 12 - to the second input of the third 21 multiplier. At the output of the quad 12

the value of -o (t - ti) is simulated (Fig. 2i),

The second input of the sixth 19 adder receives a constant voltage + U from the input 32 of the device constant. The voltage at the output of the sixth 19 adder varies from O to + 2U (Fig. 2h). A sixth 19 adder at the second time channel output 35 forms an analog model of the change in the current time within the clock period from

About to tti.

The counter 20 counts the number of periods of the clock frequency and provides a discrete value of the number of periods to the first time channel output 34 (FIG. 2g). Thus, at the outputs 34 and 35, a current time channel is formed, namely, at output 34, a discrete value of the number of clock frequency periods (Fig. 2g), and at output 35, an analogue model of the current time within the clock pulse following period (Fig. 2h). ). As a result of the action of the first clock pulse from the output 10.4 of the synchronous generator 10, the time interval to, ti is simulated at the outputs 34 and 35 of the time channel.

The first 13, the second 14, and the third 15 digital-to-analog converters (D / A) convert the values of the spline coefficient vectors Bi-i, BI, Vm. Recorded in digital form in memory blocks 7-9, respectively, into analog form.

As a result of operations performed under the action of the first clock pulse. With output 10.2 of the synchronous generator 10, the W vector is recorded in the first 7 memory block, the B0 vector is recorded in the second 8 memory block, and digital form. DACs 13, 14 and 15 convert these vectors to analog form, namely: the first 13 DACs - the vector BI from the outputs of the first 7 memory blocks, the second 14 DACs - the B0 vector from the outputs of the second 8 memory blocks, the third 15 DACs - W from the outputs of the third 9 memory block. The signals from the output of the DAC 13 are fed to the non-inverting inputs of the second 16, third 17, and fourth 18 adders. The signals from the output of the DAC 14 are fed to the non-inverting inputs of the fourth 18 adder and to the inverting inputs of the second 16 adder, the signals from the output of the DAC 15 are fed to the non-inverting inputs of the second 16 and fourth 18 adders and to the inverting inputs of the third 17 adder.

The second 16 adder summarizes the signals from the output of the D / A converter 13 with the coefficient K - from the output of the D / A converter 14 - with the coefficient from the output of the DAC 15 - with the coefficient -.

The third 17 adder sums the signals with

1 output D / A 13 - with the coefficient K y: s

output DAC 15 - with a coefficient K. The fourth 18 adder sums the signals

from the output of the DAC 13 - with a coefficient K

about

3

from the output of the DAC 14 - with a coefficient K - j,

 one

four

from the output of the DAC 15 - with a coefficient K -5-.

about

Thus, in the first cycle of operation, the second 16, third 17 and fourth 18 adders at their outputs form the following vectors in analog form: at the output of the second adder 16 EFA-1-2B0 + Bi;,

at the output of the third adder 17 0,

at the output of the fourth adder 18 0, + 6B0 + Bi.

The signals from the output of the fourth 18 adder arrive at the first input of the p 23 adder. The signals from the output of the third adder 17, multiplied by the fourth 22 uh1 knife by the value of m- (l - to) are received

on the third input of that 23 adder.

The signals from the output of the second 16 adder multiplied in the third 21 multipliers by be1

the mask (t-t0), go to the second entrance

P

p that 23 adders. As a result, at the fifth 23, the adder forms, at the information output 33 of the device, the vector of the desired process (1) according to the adopted approximation (2), (5) for the time interval t0; ti

X (t) V (t). 0,

B-1 - 2 Wo + Bi + 0.5 ()

 - B + Bi + 0.125 B-v. + 6 In + Bij.

Each (+1) -th clock pulse from output 10.1 of the synchronous generator 10 reads the i-th value of the matrices Pf U from the first memory block and from the second 2 buffer block

. the memory corresponding to the time ti.M calculates the vectors WG UBj-t

 and Pi MiBi in multiplier x 4 and 5, respectively. As a result of the 0 + 1) -th clock pulse output from 10.3 of the synchronous generator 10, 1 values of the Pf1Qi matrix are read in the third 3 block of the buffer

memory and calculating the vector BI-H (7) in the first adder 6. Under the action of (i + 1) -ro clock pulse from the output 10.2 of the synchronous generator 10, the values of the spline coefficient vector vectors are shifted: BM from the second 8 memory block in the third 9; Bi is from the first 7 memory block to the second memory block 8; HL-1 - from the first 6 adder to the first 7 block of memory. DACs 13-15 convert the values of the vectors BI + I, Bi, you, respectively, to analog form. Second 16 ,. the third 17, fourth 18 adders after the (i + 1) -ro clock pulse at their outputs form the following vectors in analog form: the second 16 adder 0.5 B-2B | + B-1; the third 17 adder 0.5 -Bi-i + Bi + i; the fourth 18 is an adder of 0.125 Vm + 6Bj + BI-M, which are fed to the first inputs of the third 21 and fourth 22 multipliers and the fifth 23 adders, respectively.

The (1 + 1) -th clock pulse from the output 10.4 of the synchronous generator 10 synchronizes the operation of the sawtooth generator 11 and writes the next unit into the counter 20, from the output of which the first output 34 of the time channel receives the number i corresponding to the i-th time interval ti: ti-i. The voltage of the sawtooth generator 11 varies from -U to

+ U, which simulates the value of r- (t - tj), is fed to the first input of the sixth 19th adder, the second input of the fourth 22 multiplier and through the quad 12 to the second input of the third multiplier. The sixth 19 adder, to the second input of which a constant voltage + U is fed from the input 32 of the device constant, generates a sawtooth-varying voltage from 0 to. + 21Г at the second output 35 of the time channel. Thus, at the outputs 34 and 35 a model of the time channel is formed, which, under the action of (i + 1) -ro clock pulse from the output 10.4 of the synchro-generator 10, simulates the time interval ti; ti + t.

SignalO, 5 (jp) 2 Bi - 1 - 2 Bi + Bi + 1 from the output of the third 21 multiplier and the signal 0.5 (-g-) 2 V | - 1 + Bi + ije output of the fourth 22 multiplier arrive respectively at the second and third inputs of the fifth 23 adder, which forms at the information output 33 of the device a model for solving the system of differential equations (1) in the form of approximation (2), (5), corresponding to the interval time ti; tn-i.

X (t). V (t) 0.5 (-) 2 Bi - 1 -2 Bi - f Bi H-1 +

+ 0.5 (% - Bi - 1 + Bi + 1 +

+ 0.125 Br-1 + 6Bi + Bi + i ,,

The advantages of splines over difference methods for the numerical solution of differential equations are that with the help of splines a global approximate solution is determined, i.e. solution defined on the whole segment. When used to approximate parabolic splines of defect 1, the second derivative has finite discontinuities, and the spline itself and its first derivative are continuous. This makes it possible to obtain a solution model in the form of a smooth continuous function of time.

Compared with other mathematical constructions, splines have better approximative properties, with equal information costs, they provide greater accuracy or equal accuracy with less informative source data.

Thus, the proposed device for modeling differential equations makes it possible to form the solution found in the form of a continuous smooth function of time.

Claims (1)

Claims An apparatus for modeling differential equations comprising first, second and third blocks of buffer memory, first and second multipliers, first, second and third blocks of memory, first adder and synchronizer, the first output of the synchronizer connected to the read inputs of the first and second blocks the buffer memory, the initial installation inputs of the first, second and third blocks of the buffer memory are connected respectively to the first, second and third information inputs of the device, the control input of synchronization the torus is connected to the start input of the device, the second output of the synchronizer is connected to the read inputs of the installation of the first, second and third memory blocks, the zero input of which is connected to the input of the initial installation of the device, the inputs of the initial installation of the first and second memory blocks are connected to the fourth and fifth information device inputs, respectively, the output of the first block of the buffer memory is connected to the first information input of the first multiplier, the output of the first adder is connected to the information input of the first block memory output the third block of buffer memory is connected to the first information input of the first adder, which is so that, in order to expand the functional capabilities by solving a heterogeneous system of differential equations with variable coefficients and forming the found solution in the form of a continuous function of time introduced into it 0 sawtooth generator, quad, third and fourth multipliers, first, second and third digital-to-analog converters, second, third, fourth, fifth and sixth adders, counter, 5 wherein the output of the first multiplier is connected to the second information input of the first adder, the third information input of which is connected to the output of the second multiplier, the first information input Which is connected to the output of the second block of the buffer memory, and the second information input is connected to the output of the first memory block and to the information inputs of the first one. a digital-to-analog converter and a second memory block, the output of which is connected to the second information input of the first multiplier and information inputs of the second digital-analog converter and the third memory block, whose output 0 is connected to the information input of the third digital-to-analog converter, the output of the first digital-to-analog converter is connected to the first inputs of the second, third, and fourth adders, 5 outputs of which are connected respectively to the first inputs of the third, fourth multipliers and the fifth adder, the output of which is an information output of the device, the output of the second digital to analog converter is connected to the second inputs of the second and fourth adders, the third input of which is connected to the third input of the second adder, the second the input of the third adder and the output of the third 5 digital-to-analog converter, the first output of the clock generator is connected to the first control inputs of the first and second multipliers / second control inputs of which are connected to the read input of the third block of the buffer memory, the third output of the first clock accumulator, the second control input which is connected to the second output of the synchronizing generator 5, the fourth output of which is connected to the synchronization input of the sawtooth generator and the counting input of the counter, the initial input Which is connected to the input Minus unit of the device, and the output is the first output of the device’s time, the output of the sawtooth generator is connected via a quadrant to the second input of the third multiplier, the output of which is connected to the second input of the fifth adder, the third input is connected to the output of the fourth multiplier, the second input of which is connected to the output of the sawtooth generator and the first input of the sixth totalizer, the second input and output of which are connected respectively to the input of the device constant and to the second output of the time channel of the device. fi% .4 b b b b b b S Ch. “O o F H