SU1275471A1 - Device for translating codes from one language to another - Google Patents

Abstract

The invention relates to computing. The aim of the invention is to extend the functionality by providing the conversion of codes with an arbitrary change, the structure of the output code sequence as compared to the input one and ensuring the transfer without changing part of the input sequence code directly to the output one. The device contains a register 1. Reception, a decoder 2 19 30 L CL 4;

Description

separators, information input 3, block 4 of associative memory, element 5 ШШ-НЕ, element 6 И, counter 7, multiplexer 8. register 9 interrogation, register 10 of mask, block 11 associative memory, element 12 ШШ, element 13 И, counter 14, decoder 15, memory block 16, register 17

Details, output 18, element 19 AND, multiplexers 20, 21, counter 22, memory blocks 23, 24, information output 25, delay element 26, trigger 27, device output 28, element 29 AND, 30 clock input, elements 31 -33 delays, 1Il.

The invention relates to computing and can be used in systems for converting and processing information, in particular, in creating high-speed operational systems, systems with interactive development mode, debugging and executing programs, hardware converters (emulators, interpreters, etc. .), in high-level language computing systems, in data bank management systems. The aim of the invention is to expand the functionality by providing conversion codes with an arbitrary change in the structure of the output sequence of codes compared to the input and ensure transfer without changing the part of the codes of the input sequence directly into the output. The drawing shows a diagram of the proposed device. The device contains a register 1 reception, a decoder 2 separators, information input 3 devices, block 4 associative memory, element IPI-NOT 5, element 6, the counter 7, multiplexer 8, register 9 poll, mask register 10, block 11 associate memory TI, Element OR 12, Element AND 13, Counter 14, Decoder 15, Memory Block 16, Register 17 All, Output 18, Device Element 19, Multiplexers 20 and 21, Counter 22, Memory Blocks 23 and 24, Information the device's output 25, the delay element 26, the trigger 27, the device output 28, the And 29 element, the device 3 clock input, and Leads 31-33 delays. The device works as follows. Before starting operation, the trigger 27 is set to the zero state, the contents of the counters 14 and 22 are zeroed out, like all cells of the memory unit 23. In block 4 of the associative memory, words are stored, the search part of each of which is the coded representation of the input word, and the information part is the convolution code of the specified input word. Thus, block 4 stores a list of input words with their corresponding convolution codes. In block F of the associative memory, words are stored, each of which consists of search and information parts, the search part is a sequence of convolution codes of the input words forming a sentence, the code of which is stored in the information part of the word. Block 16 stores information about the structure of the output sentence. This information is located in block 16, starting with a cell whose address corresponds to the offer code, and consists of a sequence of codes that are placed one in each of consecutive cells (not occupied, with two high-order bits that are marker), each of which can be a link to the input word given by the number of the input word in the input sentence (in this case, the second, starting with the senior, the bit position contains one), or a link to

3.1

an output word that has no analogue in the input, specified by the address of the output word in memory block 24 (in this case, the specified marker bit contains one), the highest mark of the word HPSHBRI is each word continuation marker in memory block 16. In block 24, the stored code representations of the output language are stored in a block, part of the cells of block 16 is not filled, and the address of the last filled cell is fixed on counter 7, the order of the word arrangement in memory block 2A is the following: each output word is located at the address corresponding to convolution code. The convolution codes of the same words in different languages may be the same.

An input sentence in the form of a sequence of characters of its components at input 3 is fed to receive register 1 and inputs to decoder 2. When a word separator (for example, a space or comma code) appears at the inputs of the last code, a single level signal is generated at its first output, which adds one to the contents of counter 22, a demand is initiated for block 4 of associative memory. If the incoming word to register 1 is contained in the list of input words (for example, in the list of service words of the programming language), then a unit level signal is generated at the corresponding search output, and the information output of block 4 reads the convolution code of the incoming word (the size of the convolution code is determined as the nearest integer, greater than or equal to the logarithm of base 2 of the number of input words), At the output of the element OR-NOT 5, as well as at the output of the element AND 6, a signal of zero level is generated, which is the convolution code ny output unit 4 through multiplexer 8, is switched on for Named register 9 survey, the appropriate bits of the mask register 10 are zero drift (corresponding to the unmasked state of the bit register homonymous rows 9). The signal from the output of the delay element 26 in registers 9 and 10 is shifted, and the convolution code (from the output of the multiplexer 8) is written to the memory unit 23 at the address 544144 with the same signal.

Counter 22 (the content of the latter corresponds to the position of the received word in the input position), i.e. In block 23, the code of the convolution of the word entered is written to the address corresponding to the position of the word in the input sentence.

If the word entered into register 1 is not in the list of words O of the input language (the specified case corresponds to the transformation of the specified word unchanged from the input to the output language, such situations arise, for example, during processing of sentences containing digital data that do not change when moving from one language to another, only their place in the sentence may change), then at the output of the element OR NOT 5 a single signal is formed that initiates the addition of the unit to the contents of counter 7, triggered by the rear frame the pulse generated at the first output of the decoder 2, and the entry of units into the corresponding bits of the register 10 of the mask (corresponds to the masking of the unrecognized word in the coded representation of the input sentence), HH4raiiM unit 0 from the output of the And 6 element of the counter 7 is transmitted (through multiplexer 8) at the input of the recording of the memory block 23 and is recorded at the address determined by the counter 22. With the same signal, the unrecognized word is written into the memory block 24 at the address specified by the contents of the counter 7.

So in block 23 in the case

The 0 word unrecognition is recorded at the address determined by the position of the word in the sentence, the cell address code of the memory block 24 in which the unrecognized word is entered.

5 Upon receipt of the subsequent words of the input sentence, the device functions in the same way until the code separating the sentences arrives at the input of the decoder 2. When the latter gets bogged out from the second output of the decoder 2, a signal is generated that sets the trigger 27 to one state and initiates a poll of the associative memory block 11

5 unmasked register bits 9.

Claims (1)

If the received sentence corresponds to one of the allowed constructions of the input language, then a single level signal is generated at the output of the SHSh 12 element, and the information output of the block 11 is recorded (the code of the linguistic structure is recorded by the signal from the output of the And 13 element and recorded to the counter 14, determined the initial construction address of the sentence on the output language in the memory block 16. Signals from the outputs of the counter 14, coming through the decoder 15 to the inputs of the memory block 16, select the first word of the output from the output signal of the AND 29 element If the word read is the last sentence in the sentence, then a zero is written in the high order (first marker), the next word is not selected, and the end of operation signal is output at output 18. If the word read by register 17 is not last in the sentence, in the first marker discharge, the z-registered unit is the one that enters the counting input of the counter 14, the contents of which increase by one, i.e. determines the choice of the next one. Thus, the register 17 sequentially reads all the constituent constructions of the output sentence, each of which is processed in the following way. The second marker bit of register 17 determines what type is recorded on the remaining (except marker) bits of register 17, If a unit contains a unit (corresponds to the fact that this part of the output sentence corresponds to a certain word of the input sentence, and the information recorded in register 17 determines the address of the input word in the input sentence), then a single signal forms AND 19 at the output of the element and permits reading from the register 17 of the convolution code of the corresponding word, which through the cartoon plexor .paet post 20 to the address input unit 24 memory to the input of which the read pos dumb signal output from the delay element 32, resulting from the output of blo ka memory 24 is read at the output 25 of the output code word corresponding to the input. Thus, if the next word in a given sentence corresponds to one of the input, then according to the number of the last one, its convolution code (or the memory, in the memory block, 24 for words that do not have a convolution code that are directly transferred to the output sentence), which defines the address of the output word in memory block 24. If zero is written in the marker register register 17 (corresponds to the situation when the next output word has no analogs in the input sentence), then the contents of register 17, except for the two most significant bits, determine the address of the output word in memory block 24, which is read in output 25 of the device. Thus, the device allows the conversion of an input code sequence to an output one with a change in the structure of the output sequence as compared to the input one. In addition, the device realizes the possibility of directly transferring a part of the codes of the input sequence to the output. Claim device for converting codes from one language to another, comprising a receive register, a decoder, a register, the first memory block, the first AND element, the OR element, the first and second delay elements, and the decoder output is connected to the address input of the first memory block The information output of which is connected to the input of the output register, the output of the second bit of which is connected by the first input of the first element I, distinguished by the fact that calling codes with an arbitrary change in the structure of the output code sequence as compared to the input one and ensuring transfer without changing part of the input sequence code directly into the output one, the first and second associative memory blocks, the separator decoder, the IPI-NE element, the second, third and quarter are entered into it And, second and third memory blocks, trigger, three counters, first, second and third multiplexers, the poll register, mask register, the third and fourth delay elements, the inputs of the reception register and the separator decoder are connected to the information input of the device, the output of the reception register is connected to the input of the first associative memory polling input, the search outputs of which are connected respectively to the inputs of the element OR NOT the information outputs of the first block of associative memory and the first counter are connected respectively to the first and second information inputs of the first multiplexer, the output of which is connected to the information the ion input of the poll register, the outputs of the poll register and the mask register are connected to the information input of the second associative memory block, the search outputs of which are connected respectively to the inputs of the OR element, and the information output is connected to the information input of the second counter, the setting input of which is connected to the output of the second element AND the first input of which is connected to the output of the OR element, the outputs of the bits of the second counter are connected to the input of the decoder, the direct output of the higher bit of the output register is connected to the account The second input of the second counter and the inverted output are connected to the output of the end of the operation of the device, the output of the second bit of the register of the sensor is connected to the control input of the second multiplexer, the outputs of the bits of the register of the issuance, except for the two high ones, the second information input of the third multiplexer is connected to the outputs of the bits of the third counter, and the output is connected to the address input of the second memory block, the output of which is connected to the second information input For the second multiplexer, the output of which is connected to the address input of the third memory block, the output of which is the information output of the device, the information input of the third memory block is connected to the output of the receive register, the recording input of the third memory block and the control input of the first multiplexer are connected to the output of the third element And, the first input of which is connected to the output of the first delay element, the input of which permits the input of the first block of associative memory, the installation input of the first counter and the counting input, t Another counter is connected to the first output of the splitter decoder, the second output of which is connected to a single trigger input, the zero output of which is the output of the device separator, a single trigger output connected to the control inputs of the second and third multiplexers and the first input of the fourth And element, the second input . which is the clock of the device, the output of the fourth element I is connected to the read input of the first memory block and through the second delay element to the second input of the first element I, the output of the second delay element through the third delay element connected to the input of the third memory block, the inverse output the high bit of the output register is connected to the zero input of the trigger, the second output of the separator decoder is connected to the installation input of the third counter, allowing the input of the second block of the associative memory and with the input of the fourth delay element, the output of which is connected to the second input of the second element AND, the output of the first delay element is connected to the recording input of the second memory block and to the enable inputs of the shift of the poll register and mask register, the output of the OR element is NOT connected to the second input The third element And, with the counting input of the first counter and with the information input of the mask register, the information input of the second memory block and the third information input of the second multiplexer are connected to the output of the first multiplexer.