SU1273917A1 - Device for taking sum of n-digit numbers - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used in the construction of summation devices and binary-decimal converters. The aim of the invention is to extend the functionality of providing conversion of a binary-to-binary code. The goal is achieved by incorporating into a multi-input sequentially summing device a group of transforming ROM blocks and a group of shift registers whose outputs are connected to the inputs of a summing device. 4 il. (L

Description

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WITH

with

The invention relates to computing and can be used in the construction of an adder for the addition of several numbers, as well as in the construction of binary-decimal converters.

The purpose of the invention is to expand the functionality involved in providing conversion of a binary-decimal code to a binary one.

FIG. 1 shows a structural diagram of the proposed device, FIG. 2 shows the contents of the memory of the permanent storage unit; FIG. 3, the contents of the memory of the associative memory block for an example of summing five five n-bit binary terms, FIG. 4 shows the contents of the memory of the permanent storage unit for the third tetrad (the bit number of hundreds of the converted binary-decimal number.

The device contains a permanent storage unit 1, an associative storage unit 2, a group elementon 3, an element 4, a group of elements 5, 6, a group 7, 8 delay elements, a group of input registers 9 and a group of constants; storage blocks 10, the first and second inputs 11 and 12 of the synchronization., the first 13 and second 14 clock inputs, information input device 15, information output 16.

The operation of the device is as follows.

According to the information inputs 15 of the device, depending on the operation to be performed, the group registers the control clock inputs 13 and 14 of the device to write to registers 9.

In the case of converting numbers from a binary-decimal number system into a binary code, the input registers from the outputs of a group of permanent storage blocks are written to the input registers by the clock signal supplied at input 13, and in the case of a sum operation of several binary numbers, the summed components in the corresponding registers 9 groups on the clock signal supplied to the input 14 of the device.

Consider the operation of the device if it performs the operation of summing several numbers.

The pulse applied to the clock input 14 directly records the summable terms from the information inputs 15 to the corresponding registers 9. When a clock pulse is fed to the second synchronization input 11 of the device, the same inputs of the And 3 group elements are given the same digits as the clock pulse determines the address of the word read from the first persistent storage unit 1. The read word from the first storage unit 1 is itself part of the sign supplied to the sign inputs of the associative storage unit 2, all bits except the best one being delayed by one clock cycle. The rest of the sign is all bits except those of the oldest bit read from the associative memory block 2 which are delayed by one clock cycle. The generated feature is additionally synchronized on the AND 4-6 elements by sending a signal on the input 12 of the device synchronization, the leading edge of which starts later, and the rear edge is ahead of the clock pulse supplied on the input 11 of the device synchronization. This measure is caused by the imperfection of delay elements 7 and 8.

In the same cycle in which the bit slice of the terms was applied at the pin 16 of the associative storage unit 2, the homogeneous output of the same name appears.

Thus, the output is the result of the summation in the sequential code, and the number of ticks for which the sum is calculated is equal to

gi) n + log, N,

where i (h) the amount spent

cycles; n is the size of the summable

addends, N - number at the same time

summable terms represented in the binary number system.

Consider the operation of the device for the case of summing five operands (see Fig. 2 and 3).

The terms are: 1. 000, 2. 011, 3.111, 4. 101, 5. 011.

The processed slices (like bits of all terms) at the first inputs of the And 3 elements of the second group will have the following form:

1. 01111, 2. 01101, 3. 00110.

During the first clock pulse applied to the synchronization input 11 of the device, to the input of the built-in address decoder of the permanent storage unit 1 (PZB 1), the lower-order bits of the summable terms, i.e. the address is 01111. At the specified address, from the Permanent Storage Unit 1, the word 011 is read in the same cycle, the first bit of which is O (sum modulo two processed slice) without delay is fed to the first input of the AND 4 element, and the remaining bits 11 group delay elements 7 are supplied to the inputs of group AND 5 of the group. Since nothing was read in the first clock cycle from the associative storage unit 2 (AZB 2), by the arrival of the first pulse at the device sync input 12, an associative feature O 00 00 is formed at the inputs of the AND 4-6 elements, and with the arrival of the pulse at the input 12 served through the outputs of the corresponding elements 4-6 to the sign inputs of block 2. Consequently, in the first cycle from block 2 the word 000 is read, the first bit of which O is the younger bit of the required amount.

During the second pulse applied to the clock input 11 of the device synchronization, a second bit of the 01101 terms is sent to the input of the built-in decoder of the address of block 1 through the corresponding elements of And 3. At the specified address from block 1 the word 101 is read, the first bit of which 1 without The supports are fed to the input of the AND 4 element and the remaining bits 10 through the delay elements 7 of the group to the first inputs of the AND 5 elements of the third group. By the arrival of the second pulse, the first input 12 of the device synchronization on the first inputs of the And 4-6 elements will form an associative feature 111 00, which with the arrival of the pulse on the input 12 is fed through the outputs of the corresponding And 4-6 elements to the sign inputs of the block 2, from which the word is read 101, the first bit of which 1 is the second bit of the required amount.

during the third pulse applied to the synchronization input 11 of the device, the third bit of the 00110 terms is fed to the input of the built-in decoder of the address of block 1 through the corresponding elements of group 3, and at the specified address from block 1 the word 001 is read, the first bit of which is O without delay is fed to the input of the element AND 4, and the remaining bits 01 through the elements 7 of the delay group to the inputs of the elements AND 5 of the group. By the arrival of the third pulse at the input 12 of the device synchronization, the associative feature O 01 01 is formed at the inputs of the elements 45 and with the arrival of the pulse at the input 12 is fed through the outputs of the corresponding elements 4-6 to the sign inputs of the associative storage unit 2 from which word 100 is read , the first bit of which O is the third bit of the required amount.

During the fourth pulse, applied to the synchronization input 11, the address 0000 at the input of the embedded address decoder of block 1 is generated as the existing bit slices have already been processed. The word 000 is read from block 1 at the specified address, and the associative feature O 01 01 is sent to the sign inputs of block 2 with the arrival of the fourth pulse at synchronization input 12, respectively, the word 100, the first bit of which O is the fourth bit, is received from the associative memory block 2. required amount.

During the first (last) pulse applied to the device synchronization input 11, the address 00000 is formed at the input of the built-in decoder of the block 1 address. At the specified address, block 000 is read from block 1 and the sign inputs of block 2 with the arrival of the fifth pulse 12 synchronization comes associative feature O 00 01, respectively, from 2 the word 001 is found, the first bit of which 1 is n -. the last (last) rank of the required amount.

Thus, 000.2 + 111 + 101 + + Ollj, -f 011, 10010. 5 Consider the operation of the device if it performs the operation of converting binary-decimal numbers into a binary code. According to the information inputs 15 of the device, the initial convertible binary number enters the corresponding address inputs of the group of permanent storage blocks, from the outputs of which the clock information fed to the 13 input of the device is sent to the block of registers. The read information is the binary terms corresponding to the decimal tetrad of the original conversion number. Thus, the further work of the device is similar to the summation of several numbers described above. An example. Let it be necessary to convert the following binary-decimal number 0010 1001), j, Q into a binary code. Each tetrad of the number to be converted is the address for the corresponding Permanent Storage Unit. The following information provided in the binary code is read at the indicated address from the corresponding permanent storage unit: the first tetrad 1001, 1001 readable information in the binary code., The second tetrad 0010, 10100 read the information in the binary code, the third tetrad 0011, 100101100 read information in binary code, the fourth tetrad 0001,111110100 readable information in binary. code. Next, we sum the resulting terms according to the algorithm described above and at the output 16 of the device in the sequential code we obtain a binary number that corresponds to the conversion operation. binary-decimal in binary The number of ticks needed to convert a n-bit binary decimal number to binary code is m log, n. 17 Formula of the invention A device for summing n-bit numbers containing a permanent storage unit, an associative storage unit, the first, second and third groups of elements And, the first and second groups of delay elements and the element And whose first input is connected to the output of the youngest bit of a permanent storage unit, the address inputs of which are connected to the top: about the respective elements of the first group, the first inputs of which are connected to the first synchronization input of the device, the second synchronization input of which dinene with the second input element And the first inputs of the elements I. second and third groups, the outputs of which are respectively connected to the polling inputs of the first and second groups of the associative storage unit, the low-bit code of which is the device output, and the group of high-order outputs through the corresponding the delay elements of the first group are connected to the second inputs of the elements AND the third group of the outputs of all the bits of the permanent storage device, except the younger one, through the corresponding delay elements of the second group We are connected to the second inputs of the corresponding elements AND of the second group, the output of the element I is connected to the polling input of the third group of the associative storage unit, characterized in that, in order to expand the functionality involved in converting the binary to binary code, a constant group is entered into it. these memorized blocks and a group of input registers, the first information inputs of which are connected to the outputs of the corresponding permanent storage blocks of the group whose inputs are connected with the inputs of the respective summable device numbers and with the second information inputs of the corresponding input registers of the group, the outputs of which are connected to the second inputs of the corresponding AND elements of the first group, the first and second control recording inputs and the synchronization inputs of all input registers are connected respectively to the first and second recording control inputs device and the first synchronization input device.

FIG. 2

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Claims (1)

Formula Row numbers device, memory block, memory block, third group of AND elements, second group of delay elements, and AND element, the first input of which is connected to the low-order output of the permanent memory block, whose address inputs are connected to the outputs of the corresponding elements of the first group, the first inputs which are connected to the first synchronization input of the device, the second synchronization input of which is connected to the second input of the element AND and the first inputs of the elements I. the second and third groups, the outputs of which correspond are connected to the polling inputs of the first and second groups of the associative storage unit, the low-order output of which is the output of the device, and the group of high-order outputs through the corresponding delay elements of the first group is connected to the second inputs of the And elements of the third group, the outputs of all the bits of the permanent storage device, except the low-order, through the corresponding delay elements, the second second inputs of the cops And the second one And connected to the group of the associative storage unit, characterized in that, with In order to expand the functionality that provides the conversion of a binary decimal code to binary, a group of read-only memory blocks and a group of input registers are introduced into it, the first information inputs of which are connected to the outputs of the invention to summarize the n-containing constant, associative, second, first and second groups connected to the corresponding eleggroup, the output element of the input polling third Next, we summarize the obtained terms in accordance with the algorithm described above, and at the output of the device 16 in the serial code we get a binary number that corresponds to the operation of converting 50 binary decimal numbers to binary code. The number of clock cycles required for converting an η-bit binary decimal number to binary code is 55 equal to constant memory blocks of the group, the inputs of which are connected to the inputs of the corresponding summed numbers of the device and to the second information inputs of the corresponding input registers of the group, the outputs of which are connected to the second inputs of the corresponding elements And the first group, the first and second control inputs of the record and the synchronization inputs of all input registers are connected respectively to the first and second inputs s recording control device and m = log ₂ (40 9 ^r '+ log ^ n. the first input of the device synchronization.