SU1261120A1 - Bipolar code generator - Google Patents

Description

The invention relates to computing technology and can be used in discrete information transfer systems.

The purpose of the invention is to enhance the functionality by generating a para-phase signal.

The drawing shows a schematic diagram of the shaper.

The shaper of the bipolar code contains the first, second, third and fourth transistors 1-4 of the first conductivity type (in the drawing Р-П-Р), the first and second transistors 5 and 6 of the second conductivity type (in the drawing п-Р-п) , first to sixth resistors 7-12, first and second resistive dividers 13 and 14, first and second elements 15 and 16 2I-OR-NOT one-one 17, first and second delay elements 18 and 19, first and second elements 20 and 21 And, the first and second threshold elements 22 and 23, clock input 24, the first and second information inputs 25 and 26, the first and second w us 27 and 28, a power source, first and second outputs 29 and 30 of the device. Threshold elements 22 and 23 are triggers.

The device works as follows.

In the initial state, in the absence of clock pulses, which corresponds to the logical O on the clock input 24, the output of the one-shot 17 also contains the level of the logic O, the first and second logic elements 15 and 16 2I-OR-NOT are locked to all inputs, and on their outputs logic level 1 is present. All transistors 1-6 are locked, signals at outputs 29 and 30 are absent. The presence of signals 1 at information inputs 25 and 26 does not affect the state of the device.

The leading edge of the output pulses is formed in this way. When a clock pulse arrives in the form of logic level 1 at clock input 24 and if logic level 1 is present, the first information input 25 triggers the first element 15 2I-OR-NOT and a logical O appears at its output. The current through the divider 13 unlocks the third transistor 3 RPN, its current unlocks the first transistor 1 RPN and. the second transistor 6PPp, at the first output 29, the potential of the positive power supply bus 27 appears; at the second output 30, the potential of the negative power supply pin 28. The state of logical 1 is set at the output of the first threshold element 22, and the state of logical O is set at the output of the second threshold element 23.

The falling edge of the output pulses is formed as follows. After the end of the clock pulse and the appearance of a logical O at the clock input 24, the first element is closed AND AND the first element 15 ZI-OR-NOT, the logical element appears at its output

 one

lock the third and the first

transistors 3 and 1 PPP and the second transistor 6 ppP. At the first information input 25, logical O may appear, but from the output of the first delay element 18, the potential of logical 1 continues to flow to the first input of the first element 20 I, the second input of which receives logical 1 from the first threshold element 22. Logical 1 from the output of the first element 20 And goes to the second input of the second element And the second element 16 2I-OR-NOT. On the falling edge of the clock pulse, a single pulse 17 is triggered and a positive pulse is output with a logic level 1 to the first input of the second element AND the second element 16 2I-OR NOT. Element 16 opens, a logical O appears at its output. The current through the second divider 14 unlocks the transistor 4 PnP with a quarter, its current unlocks the second transistor 2 Ppn and the first transistor 5ppp. The first output 29 is connected to the negative power bus 28, the second output 30 is connected to the positive power bus 27. There is a quick reload of parasitic capacitances connected to outputs 29 and 30. When a potential near the first output 29 is reached, the first threshold element 22 is thrown, a logical O appears at its output, and the first About the output of which closes the second element 16 2I-ШШ-НЕ, At the same time, the fourth and second transistors 4 and 2 PpP and the first transistor 5 ppp are locked and the neutral is restored312611

The first and second outputs are 29 and 30.

The pulse length of the one-shot 17 is chosen slightly longer than the length of the formed rear edge of the output pulses and less than the length of the clock pulse. After the termination of this pulse, the pattern of the formation of the trailing edge of the pulses is locked and does not affect the formation of the leading edge of the pulses. The delay time of the first and second delay elements 18 and 19 is chosen greater than the duration of the single-vibrator 17 and less than the duration t5 of the clock pulse, so that the change of information does not affect the operation of the formation of the trailing edge of pulses.

When a logic level 1 appears at the second information input -20 26, the circuit operates in the same way, but the leading edge of the pulses is formed using the second element 16 2I-OR-NOT, the fourth and second transistors 4 and 2 RP-P-P and the first 25 of the resistor 1 nPp, and the back front - using the second delay element 19, the second element 21I, the second threshold element 23, the first element 15 2I-OR-NOT, the third and first transistors 3 and 1 P- pp, second transistor 6 ppp.

Claims (1)

Invention Formula 35 Bipolar code generator, containing two transistors of the first conductivity type and two transistors of the second conductivity type, two elements And six transistors, bases 40 of the first transistors of the first and. of the second type of conduction, respectively, the first and second resistors are connected respectively: to the first and second buses of the power supply, and their 45 collectors are connected and through the third resistor are connected to the first output of the device, and the first and second resistive voltage dividers, t , with the purpose of expanding the functionality by forming a paraphase signal, the third and fourth transistors of the first conductivity type are introduced into it, the first and second delay elements 55, one-shot, first and second second threshold elements, the first and secondary p-th elements 2I-OR outputs HE5 koto04 through the respective resistive voltage dividers connected to the first power supply bus, the base of the first transistor of the first conductivity type is connected to the emitter of the third transistor of the first conductivity type, the base of the second transistor of the first conductivity type is connected to the emitter of the fourth transistor of the first conductivity type and through the fourth resistor - the first bus power source, the base of the first transistor of the second conductivity type with the collector of the fourth transistor of the first conductivity type, the base of the second transistor of the second conductivity type is connected to the collector of the third transistor of the first conductivity type and through the fifth resistor to the second power supply bus, emitters of the first and second transistors of the first conductivity type and emitters of the transistors of the second conductivity type are respectively combined and connected respectively to the first and the second power supply buses, the bases of the third and fourth transistors of the first conductivity type are connected to the middle terminals of the first and second resistance cases, respectively Voltage collectors, the collector of the first transistor of the first conductivity type is connected to the input of the first threshold element, the collectors of the second transistor of the first and second conductivity types are combined and connected to the input of the second threshold element and through the sixth resistor to the second output of the device, the first inputs of the 2I-OR- NOT combined with the one-shot input and connected to the device's clock input, the second inputs of the first and second elements. 2I-SH1I-NOT are combined with the inputs of the corresponding delay elements and connected to the corresponding with (the device information inputs, the output of the one-shot is connected to the third, the inputs of the elements 2I-OR-EE, the outputs of the delay elements are connected to the first inputs of the corresponding And elements, the second inputs of which are connected to the outputs of the corresponding threshold elements, the output of the first and second elements And are connected to the fourth inputs of the second and first elements 2I-OR-NO, respectively.