SU1457149A1 - Output stage of pulse shaper - Google Patents

Abstract

The invention relates to a pulse technique and can be used in devices for generating pulse signals of the nanosecond and subnanosecond ranges. The aim of the invention is to expand the ranges of formation of the upper and lower levels of voltage, the accuracy and stability of the installation.

Description

one

The invention relates to a pulse technique and can be used in devices for generating pulse signals of the nanosecond and subnanosecond ranges.

The aim of the invention is to expand the ranges of formation of the upper and lower levels of voltage and increase the accuracy and stability of the output voltage setting, increasing the speed.

The drawing shows a diagram of the output stage of the pulse shaper.

The output stage includes the first and second channels of the formation of the upper and lower levels, respectively, which contain the first 1 and 2 and second 3 and 4 keys, implemented on transistors 5 and 6, the combined emitters of the first and second transistors 7 and 8 of the first key 1 of the first channel through the first a resistor 9 is connected to the first power bus 10, the combined emitters of the first and second transistors 11 and 12 of the first switch 2 of the second channel are connected via the second resistor 13 to the second power bus 14, and the collector of the transistor 7 is connected to the first connection point first and second diodes 15 and 16, the collector of transistor 11 is connected to the connection point of the third and fourth diodes 17 and 18, the bases of transistors 5 and 6 of the second keys of the first and second channels are connected, respectively, to the third resistor 19 to the first bus 20 of the reference voltage and through the fourth resistor 21 — with the second bus 22 of the reference voltage, the third key 23 of the first channel and the third key 24 of the second channel.

The third key 23 of the first channel

contains two diodes 25 and 26, a resistor 27 and a transistor 28 with a conductivity opposite to that of the second switch of the given channel. The third key 24 of the second channel contains two diodes 29 and 30, a resistor 31 and a transistor 32. The collectors of the first and second transistors 7 and 8 are connected via resistors 33 and 34 with

INNOVATIVE 14. The collectors of the first and second transistors 11 and 12 through resistors 35 and 36 are connected to bus 10. The bases of the first and second transistors of both channels are connected to the first, second, third and fourth inputs 37-40 of the device, respectively. The device includes an output bus 41.

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The output stage operates as follows.

If the input 37 voltage logical 1 negative polarity, the input 40 voltage logical 1 positive polarity,

 The inputs 38 and 39 are the logic voltage O, the voltage on the second bus 22 of the reference voltage (voltage of the lower level) and negative polarity, and the voltage on the bus 20 of positive polarity (voltage of the upper level bg), then transistors 8 and 11 are open, and transistors 7 and 12 are closed. Since transistor 8

is open, and the voltage on the bus 20 is positive, then the transistor 28 is open

The mode of the transistor 8 is set so that the transistor 28 closes when the voltage on the bus 20 is close to zero. The mode of the transistor 11 is set in such a way that the transistor 5 is opened only when the voltage on the bus 20 is close to zero, therefore, when the voltage on the line 20 is positive, the transistor 5 is closed. Since the transistor 12 is closed, the transistor 32 is also closed. By the negative voltage across the bus, 22, the transistor 6 is closed. The voltage of the upper level of positive polarity on the output bus 41 is determined by the voltage difference across the bus 20 and the collector-emitter voltage of the open transistor 28. If you change the polarity of the voltage on the bus 20 to negative, the transistor 28 closes, opens the transistor 5 and on bus 41 will form a negative voltage at the upper level.

Since transistor 28 is saturated in the entire positive voltage region and closes only when the voltage U g on the bus 20 is close to zero, and in the whole range the change in the positive polarity Ug is determined only by the output transistor 28

In the negative range of voltage Ug on bus 20, speed is determined only by transis: by tor 5, which is part of

when the voltage Ug is close to zero, and is in this mode in the entire region of negative voltages Ug

If the inputs 37 and 40 are the voltage of the logical O, the input 38 is the voltage of the logical 1 negative polarity, the input 39 is the voltage of the logical 1 positive polarity, the voltage of the lower level Uc on the bus 22 of the negative polarity, and The upper level Ug on the bus 20 has a positive polarity, so that transistors 7, 12, and 32 are open, and transistors 8, 11, 28, 5, and 6 are closed. The formation of the lower level on the output bus 41 occurs similarly to the formation of the upper level. The voltage of the lower level on the output bus is determined by the difference in voltage

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bus 22 and the collector-emitter of the open transistor 32. If the polarity of the bus voltage 22 is changed to positive, the transistor 32 will close at voltage and close to zero, a transistor 6 will open on the output bus 41 lower level

Claims (1)

Invention Formula The output stage of the pulse generator containing the first and second channels of the upper and lower levels, respectively, connected to the output bus, each of which includes the first key made on two transistors according to the current switch circuit and the second key made on one transistor, the combined emitters of the first and the second transistors of the first key of the first and second channels, respectively, through the first and second resistors are connected to the first and second power buses, respectively, the collectors of the first transistors of the first key, respectively, of the first and second channels are connected to the connection points of the first, second, third and fourth diodes, respectively, the second electrodes of which are connected to the base and collector of the second switch of the second channel and the base and collector of the transistor of the second key of the first channel, base of transistors the second keys of the first and second channels are connected, respectively, via the third resistor to the first reference voltage bus, and the fourth resistor is connected to the second reference bus on splicing, the conductivity of the transistors of the first key coincides with the conductivity of the transistor of the second key of the given channel and opposite to the conductivity of the transistors of the first key of the second channel, characterized in that in order to expand the formation ranges of the upper and lower voltage levels and improve the accuracy and stability of the output voltage, speed increase, a third key is inserted into each channel, which is executed symmetrically to the second key and consists of a zug. diodes, resistor and transistor with 5U571A96 conductive, opposite pro-keys of their channels, collectors power transist, ora of the second key transistors of the first keys are connected of this channel, the emitter and collector through the corresponding resistors, the third key's transistor of the third pins whose connectors are combined and sub-respectively with the emitter and the number of keys to the second and the transistor lecturer of the second key, the first power supply buses, the base of the first of the channel, common points of the diode and the second transistors of both channels the third keys of the first and second ka are connected respectively with the first, The lines are connected to the QOL-Q second, third and fourth entrances lecturers second transistors of the first device.