SU634374A1 - Analogue storage - Google Patents

Description

pvt transistors, limited accuracy in storage mode, unipolarity of the circuit and low input resistance determined by the resistors used at the input. The circuit of the invention is to increase the accuracy and speed of the device. The goal is achieved by the fact that it additionally contains eight, transistors, the base of the seventh, eighth, and tenth transistors are connected to one of the capacitor plates, the base of the fifth and sixth transistors are respectively connected to the emitters of the seventh and eighth, ninth and tenth with the bases of the eleventh and twelfth transistors and with the outputs of the current generators, the emigres of the eleventh and twelfth transistors are connected respectively to the collectors of the ninth and the eighth transistor in, the inputs of the generators are current connected to the gate gate pulse, the thirteenth transistor collector and the fourteenth transistor collector are connected to the negative and positive power lines respectively, the emitters of the thirteenth and fourteenth transistors are connected to the bases of the first and second transistors and through the resistor to the device input, the base of the thirteenth traistor is connected to the bases of the first and second transistors the eighth transistor, and the base of the fourteenth transistor is connected to the emitter of the ninth transistor. The invention is illustrated by the drawing, which shows the electrical circuit of the device. The device contains current generators 1 and 2, transistors 3,4,5 and b, forming an emitter follower, transistors 7-16, with transistors 7,9,10,13 and 15 forming one of the control arms, and transistors 8.11, 12.14 and 16 are another control shoulder, capacitor 17, with pairs of transistors of different types of conductance 9-10 and 11-12 representing two-sided voltage limiters relative to the voltage on the capacitor 17, and transistors 7 and 8 are intended for switching modes of operation of the device, which also contains a zero potential bus 18, a strobe bus pulse 19, resistors 20, 21 and 22, positive 23 and negative 24 wiring. The device works as follows and has two modes of operation. First of all, it is a buffer device with a high input to the aloe output resistance. In this case, the voltage acting at its input, OR, is traced on the capacitor 17, which is its output. In the second mode, the device performs the function of an open key, while on the capacitor 17, the voltage that was on it at the moment of switching from the first mode to the second is saved. These modes of operation of the device are determined by the potential supplied to the gate pulse bus 19. When there is a resolving potential on the bus, the current generator 1 outputs a current + Y flowing into the emitter of transistor 9, and a current generator 2 - flowing from the emitter of transistor 12 transistors 9 and 12 are open. In this case, the transistors 3.4 and 5.6 will be open, and the transistors 7,8,10,11,13 t 16 are completely closed. The emitter follower on transistors 3,4,5 and 6 in this mode is closed to capacitor 17 and therefore the voltage on it monitors the input voltage. When a forbidding potential is applied to the bus of the gating pulse 19, a synchronous change in the polarity of the currents of the generators 1 and 2 occurs without changing their value. At the same time, transistors 9 and 12 are locked, and a transistors 10 and 11 are opened. The potential in the junction of the emitters of transistors 9 and 10 drops by approximately 1.4 volts, while at the connection point of the emitters of transistors 11 and 12, it increases at the same time by approximately 1.4 volts. The magnitude of these drops, acting synchronously, is quite sufficient for very fast locking of all four transistors of the emitter follower (on transistors 3,4,5 and 6), which makes it impossible to further change the charge on the capacitor 17. At the same time the collector circuits of the transistors 10 and 11 of the eye are connected to the voltage on the capacitor 17 through open transistors 14 and 13 which are used as floating power sources, repeating the voltage on the capacitor 17. The last circumstance a quantity of base currents 10 and 11 is propelling leakage current of the capacitor 17, and hence is a possibility of compensation of the leakage current. In addition, in this mode, there is a closed circuit consisting of transistors 10, 11, 15, and 16. Thus, the voltage from the capacitor 17 is applied to the resistor 22. The voltage divider formed during this, consisting of the resistor 22 and the input resistance of the circuit , allows the division factor of the divider to reduce the error determined by the passage of the input instantaneous value of the signal. Since the opening of the emitter follower is accomplished by closing the emitter currents of transistors 3 and 4, as well as the base currents of transistors 5 and 6, into the emitter circuits of the opening transistors 7 and 8, respectively, controlled in turn by small and fast voltage drops applied to their bases , then the opening time, determined mainly by the time, is necessary: for dissolving accumulated minority carriers in the bases of transistors 5 and 6, it turns out to be very insignificant. This provides aperture uncertainty on the order of 1 NA. A full three symmetry schemes with zero-level control ensures operation from bipolar input signals. The proposed device provides technical characteristics at low power dissipation, which makes it possible to produce it using the methods of hybrid and integrated technology and causes a high technical and economic efficiency of application. Analog memory device containing six transistors, the first four of which are connected by bridge circuit, the bases of the first and second transistors are combined, the emitters of the third and fourth transistors are connected to one of the capacitor plates and the output of the device, the other capacitor plate is connected to the bus the zero potential, the emitters of the fifth and sixth transistors are connected to the bases of the third and fourth ground strings, respectively, the resistor, the gate pulse bus and the current generators, In order to increase accuracy and speed up, it additionally contains eight transistors, the base, the seventh, eighth, ninth and tenth transistors are connected to one of the capacitor plates, the base of the fifth and sixth transistors are respectively connected to the emitter the seventh and eighth, ninth and tenth, with the bases of the eleventh and twelfth transistors and with the outputs of the current generators, the emitters of the eleventh and twelfth fanzistors are connected respectively to the collectors of the ninth and eighth tranz tori, the inputs of the current ator gene are connected to the gate pulse bus,. thirteenth transistor collector and fourteenth transistor collector, connected to negative and positive power lines, respectively; the thirteenth emitter and fourteen transistors are connected to the bases of the first and second transistors and through the resistor to the device input, the base of the thirteenth. The transistor is connected to the emitter of the eighth transistor, and the base of the fourteenth transistor is connected to the emitter of the ninth transistor. Sources of information received during the examination: 1.IEEE Tt-ans.on Circuit Theory, 1964, V. CT-11, NO 3, p. 38J-396. 2. Instruments and Experimental Technique, 1972, No. a, p. 1O7-1O9. 3. USSR author's certificate NO 484637, cl. N OZ K 13/02, 17,02.73

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