SU767959A1 - Delay device - Google Patents

Description

(54) DELAY DEVICE

one

The invention relates to the field of pulsed technology.

A delay device is known that contains a clock capacitor, the charge of which is produced from a current generator, and the discharge is an output emitter follower of the emitter-coupled logic trigger valve (ECL). Valve ECL element is used as a threshold device. This device has two significant sources of instability in the delay time of the pulse front, which manifests itself with changes in ambient temperature and supply voltage. Under the influence of destabilizing factors, the initial level of the voltage on the timing capacitor changes, moreover, the level of the input voltage changes, at which the logic gate acts as the threshold device C {3.

. The aim of the invention is to increase the stability of the delay of the pulse front under the influence of destabilizing factors (due to changes in the environment and supply voltage).

To achieve this goal, a delay device containing a triggering valve, a current source connected between the power supply and the forward output of the triggering valve, a circuit consisting of a series-connected resistor and a timing capacitor, connected between the forward output of the triggering valve and the ground bus, the threshold element A second current source is connected between the power bus and the inverted input of the differential receiver as a threshold element, the direct input of which is connected to an ungrounded drive. masonry clock co-sensor, a resistor connected between the inverse input of the differential receiver and the inverse output of the gate valve.

The drawing shows the principal circuit diagram of the delay device ..

Claims (1)

It includes a valve I triggering an ECL 20 with a complementary output. The direct output of the valve 1. through the resistor 2 discharges the timing capacitor 3, the charge of which is carried out by the current of the current source 4. The timed capacitor is connected between the ground bus and the direct input of the differential ECL receiver 5, which is a threshold element. The inverted input of the differential receiver 5 through the resistor 2 is supplied with the signal from the inverted output of the triggering valve 1. The current through the resistor 6 is supplied from the HELP of the current source 7, similar to the current source 4. In the initial state, the triggering ECL valve is in the logical zero state, A suitable voltage level is maintained on the timing capacitor. The inverted input of the differential receiver maintains a voltage level equal to the logic unit level plus the voltage drop across the resistor 6 from the current of the current source 7. When the ECL triggering valve switches to the logical unit state, the timing capacitor 3 begins to charge with the full current of the source 4, because the output current the transistor at the direct output of the ESL triggering valve is closed. At the inverted input of the differential receiver, a potential is set equal to the voltage of a logical zero plus the voltage drop from the current of source 7 at resistor 6. It is obvious that the voltage at the direct and inverse inputs of the differential receiver is compared when the increment of voltage at the clock capacitor 3 becomes equal to the voltage drop across the resistor 6. At this point in time, the differential receiver will switch and a delayed voltage drop (pulse front) will form at its output. A change as a threshold element of a differential receiver ensures the appearance of the output signal at the moment of equality of the potentials at its forward and inverse inputs regardless of the absolute 3: Start of these potentials. Thus, the stability of the delay time under the influence of destabilizing factors is determined by the stability of the potential difference of a logical zero on the forward and inverse outputs of the triggering valve, which is ensured by using the complementary outputs of the same valve, as well as the stability of the current sources 4 and 7, which achieved by using transistors with matched parameters as active elements of these sources. The use of new elements - a differential receiver as a threshold device for a circuit consisting of a resistor connected between the inverter output of the triggering valve and the inverter input of the differential receiver, and a current source connected between the power supply and the inverter input of the differential ECL receiver favorably distinguishes the proposed front delay circuit impulse from prototype. The instability of the delay time of the prototype device is 1% when the supply voltage varies by 5% from the nominal value and when the ambient temperature changes from 5 to 60 ° C, whereas the proposed device instability of the delay time does not exceed 0.2% when changing supply voltage in the same range. The instability of the delay time when the ambient temperature varies from 5 to 60 ° C is not more than 1%. Thus, the proposed scheme allows to obtain characteristics of the stability of the delay time more than 5 times better than that of the prototype, and is a precision electronic time delay circuit. The invention A delay device comprising a triggering valve, a current source connected between the power bus and the forward output of the triggering valve, a circuit of a series-connected resistor and a timing capacitor, connected between the forward output of the triggering zentil and the ground bus, the threshold element characterized by that, in order to increase stability, a second current source is inserted in it, which is connected between the izina power supply and the inverse input of the differential receiver as a threshold element, second input of which is connected to an ungrounded plate of Timing capacitor, a resistor connected between the inverted input of the differential receiver and the inverted output gate triggering. Sources of information taken into account in the examination 1. Lebedev A. V. and others. The formation of time intervals with the help of integral E. SEM chip. "Questions of radio electronics, a series of EVT, vol. I, 1975 (prototype).