SU1190359A1 - Comparator - Google Patents

Abstract

COMPARATOR, containing a synchronization bus, two / 5-flip-flops, main and additional, each of which is made on two transistors of the first conductivity type, a gating transistor, the collectors of which are connected to the bases of the transistors of the main / 5-flip-flop, first and second input transistors of the second conductivity type The bases of which are connected to the zero potential bus, the emitters respectively to the first and second input buses, and the collectors to the bases of the main / 5-flip-flop transistors, the second collectors of which cross under Connected to the bases of the transistors of the additional RS trigger, the second collectors of which are connected to the first and second output buses, characterized in that, in order to increase the sensitivity and speed by reducing the influence of the nodal capacitances, a 5-flip-flop is introduced into it, conduction, the first input of which is connected to the third switches of the first transistor of the main / 5-flip-flop and the first transistor of the additional / 5-flip-flop, and the second input to the third collectors of the second transistor core / 5 flip-flop and a second additional transistor / 5 flip-flop, wherein the gate of the transistor emitter soediel nen bus to zero potential, and the base - with the synchronization bus. co 00 00

Description

The invention relates to a pulse technique and can be used to build elements for comparing analog-digital converters.

The aim of the invention is to increase the sensitivity and speed by reducing the influence of nodal capacities.

The drawing shows a schematic diagram of a comparator.

The comparator contains RS triggers 1 and 2, the main and additional, each of which is made on two transistors 3-6 of the first type of conductivity, and a gate transistor 7, the collectors of which are connected to the bases of transistors 3 and 4 of the main RS trigger 1 and to the collectors of the first and the second input transistors 8 and 9 of the second conductivity type, emitters connected respectively to the first and second input buses 10 and 11, while the second collectors of transistors 6 and 7 of the additional RS-trigger 2 are connected to the first and second output buses 12 and 13, and RS -tr gger 14 formed on the transistors 15 and 16 of the first conductivity type, a first input of which is connected to the third collector of the first transistor 3 of the main RStriggera first transistor 1 and 6 additional RStriggera 2 and the base of the second transistor 7 is connected to the synchronization bus 17.

The comparator operates as follows.

In the initial state (high potential on the synchronization bus 17), transistor 7 is open, transistors 3 and 4 are closed, RS-flip-flops 2 and 14 store information. Suppose that transistors 5 and 16 are open, transistors 6 and 15 are closed, the potential on the first input bus 10 is greater than the potential on the second input bus 9. When the negative clock edge arrives on the synchronization bus 17, the gate transistor 7 closes, the transistors 9 and 8 start charge the nodal capacitances C _{5zy ί} (18) and C _{Sia 2} (19). Since the charge current of node 18 is greater than the charge current of node 19, the first transistor 3 will open first, the second, third, sixth transistors 4, 5 and 15 will close, the fourth transistor 6 will open, the seventh transistor 16 will close, the information recorded in the additional RS-trigger 2, will change.

At the moment of arrival of the positive edge of the clock pulse, the fifth transistor 7 will open, the first and second transistors 3 and 4 will close, the sixth transistor 15 will open, triggers 1 and 2 will store information until the next negative edge of the clock pulse arrives.

Thus, a higher voltage on the input bus 10 leads to the appearance of a logical unit on the first output bus 12 and a logical zero on the second output bus 13, i.e., this circuit performs the function of a comparator _{5 of the} input signals supplied to the input buses 10 and 11.

The sensitivity of the known device to the input signals is determined by the width of the hysteresis loop, due to the dependence of the capacitance of the collector junction of the transistor on the voltage applied to it, i.e., the dependence of these capacitance nodes. ι and surrendered. 2 from the information recorded in the second RS-trigger 9:

Cyan. i == Co + KCksh-p-n (UQ); 15 Passed. 2 = Co4-K.Skb'n.-r-Ts (UQ);

Co - Sk8p-Ya-p4-C <5 ₉ n-P-L + Cxfi'NpM _j where K is the coefficient of proportionality;

Uq, Ug - signal value at the outputs ^{20 of the} main RS-trigger 1;

CjiSp-xp, C ^ eu-r-x, C _K ^ yf> -x _{5 are the} capacitances of the transitions of the transistors pp-pp and p-pp, respectively.

Since the outputs of the main RS-flip-flop 1 _{25 of} the known one are connected to the inputs of an additional RS-flip-flop 2, which stores information at the time of comparison, the capacities of the nodes Su _m ί and С _{53Л #} 2 turn out to be different, and this difference is not constant, but depends from the state of the second trigger. ³⁰ The proposed comparator provides more accurate equality of the nodal capacities, since each transistor of the main RS-trigger 1 has two collectors, one of which is at high potential at the time of comparison and the other at low. Thus, the effect of the dependence (U) on the nodal capacities of Suzd. ί and S bond. 2 weakened, the hysteresis loop decreases, the sensitivity increases (5-10 times).

The speed of the comparator depends on the difference between the input signals. The presence of a hysteresis loop is reflected in the fact that, depending on the information stored in the second trigger, the same difference 45 in the input currents leads to an unstable difference in the charge speeds of the Susa nodal capacities. ! and Cyyt. 2, i.e., to a different transient rate.

The proposed comparator has a 5-10 times smaller hysteresis loop, therefore, with a small difference between the input signals, comparable with the width of the hysteresis loop, its speed will be 5-10 times less, and is intended to be implemented as part of integrated circuits with injection power.

VNIIIPI Order 6982/51 Branch of the PPP "Patent",

Circulation 862 Subscription

Uzhhorod, st. Project, 4

Claims (1)

A COMPARATOR containing a synchronization bus, two PS-flip-flops, the main and additional, each of which is made on two transistors of the first type of conductivity, a gate transistor, the collectors of which are connected to the transistor bases of the main PS-trigger, the first and second input transistors of the second conductivity type, base which are connected to the zero potential bus, emitters, respectively, to the first and second input buses, and the collectors to the transistor bases of the main PS trigger, the second collectors of which are cross-connected s to the bases of the transistors of the additional PS trigger, the second collectors of which are connected to the first and second output buses, characterized in that, in order to increase the sensitivity and speed by reducing the influence of node capacitances, a PS trigger made on transistors of the first type of conductivity is introduced into it, the first input of which is connected to the third switches of the first transistor of the main PS-trigger and the first transistor of the additional PS-trigger, and the second input - to the third collectors of the second transistor of the main PS- rigger and second additional transistor PS-flop, wherein the gate of the transistor emitter is connected to zero potential bus, and base - to bus synchronization. P to