SU1257850A1 - Device for converting number from residual class system code to position code - Google Patents

Abstract

This invention relates to the field of computing. The aim of the invention is to improve the speed. The goal is achieved in that a device comprising a position counter, subtracting modular counters, two elements AND, two elements OR, trigger, contains; the third element AND with the corresponding connections. 1 il. (/)

Description

The invention relates to computing and can be used to interface with computations with devices operating in the system of residual classes (juice), as well as in data transmission equipment using JUICE codes.

The purpose of the invention is to increase speed.

The drawing shows a device diagram for converting a number from the system of residual classes to a position code.

The device contains a position counter 1, subtracting modular counters 2 ,, 2 j. . . 2, elements ШШ 3 and 4, elements И 5, 6 and 7, trigger 8, clock input 9 of the device, input 10 for starting the device, output 1 for the device.

Position counter 1 allows to increase the number contained in it by one or given, for it the constants q, n P-- and q ,; modular counter 2f, - reduce the number contained in it by one or set-up

for it are constants f, 1 P P;

 li-l

In-i I П P; | moJ Р, - and a modular counter

2., - reduce by one or

the constant defined for it.

Each of the subtractive modular counters 2 ,, 22, .i produces an account modulo the corresponding base in the RNS code.

A device for converting a number from a system of residual classes to a positional code works as follows.

At the initial moment of time, the counter 1, the trigger 8 is set to the zero state. In modular counters 2, the number to be converted is written in the SOC code.

According to the Start signal, fed to input 10, the trigger 8 is set to a single state. Logic} from the trigger trigger 8 goes to the second inputs of the AND 5-7 elements, the first inputs of which are clocks.

If the contents of the modular meters 2, 2j, ..., 2n.2 are not equal to zero, t

5 Q

five

0

five

0

five

0

five

a single signal from the direct output of the element OR 3 allows the passage of clock pulses through the AND 5 element to the single counting inputs of counter 1 and modular counters 2, and a zero signal from the inverse output of the element OR 3 prohibits the passage of clock pulses through the elements 6 and 7. Under the action of the clock pulses, the counter 1 and the modular counters 2 begin to change their state by one with the arrival of each clock pulse. At the time of zeroing

modular counters 2,,

the zero signals from their outputs go to the inputs of the OR 3 element and produce a zero signal at its direct output, which prohibits the passage of AND 5 clock pulses through the element. From the inverse output of the element OR 3 to the third inputs of the elements And 6 and 7 receives a single signal.

If the content of modular counter 2 is not zero, then a single signal from its inequality output. The content zero allows the passage of clock pulses through the AND 6 element to the second counting inputs of counter 1 and modular counters 2 п ,, and 2, respectively, the base Р „, and P, and RP R.,, and the zero signal from the output of equality to zero of the content of the modular counter 2j, prohibits the passage of clock pulses through the element And 7.

The arrival of one clock pulse to the second INPUT of the counter 1 causes an increase in the state of this counter by a given constant q, and the arrival of the clock pulse to the second inputs of the modular counters 2f, -, and 2 - a decrease by the value of f I. When resetting the modular counter 2., the zero signal from its output of the inequality zero contents of the element And 6, and the unit

The signal from the output of equality to zero of the content received at AND 7 permits the passage of clock pulses to the third inputs of counter 1 and the modular counter 2, and the arrival of one clock pulse to the third input of counter 1 causes the counter to increase by a constant q, and the arrival the clock pulse to the third input of the modular meter 2c is a decrease by the value of t.

At the moment of zeroing of the modular counters 2 and 2 "., And the arrival at the input of an OR 4 element of a zero signal from an OR 3 element, the inverse output of the OR 4 element produces a single signal that sets trigger 8 to the zero state.

At this point, the conversion of the number from the SOC code to the binary code ends with, and the result of the conversion is on counter 1.

Claims (1)

Invention Formula A device for converting a number from the system of residual classes to a position code containing a position counter, and subtractive modular counters (where c is the number of bases P, -P, and P, P, ... P .... P., P. "), Two AND elements, two OR elements, a trigger, the device clock input connected to the first inputs of the first and second AND elements, the second inputs of the short-circuits connected to the trigger output, the unit input of which is the device start input, the output of the first AND element connected to the counting inputs of the first (ii-2) -x subtractive modes lnyh counters, with the first count input of the counter and the position (n-l) -th and r -th modular subtracting counters, the output of the second member and coupled to the second count input. position counter and I subtract j Yu 15 20 25 -jg five modular counter, the position counter output is the output of the device, the inequality outputs zero content of the first (p-2) -s and subtractive modular counters are connected to the corresponding inputs of the first OR element, the direct output of which is connected to the third input of the first element AND with the first input of the second OR element, the second input of which is connected to the output of the zero inequality of the contents of the h-th modular subtractive counter, the inverse output of the second element OR is connected to the zero input of the trigger, the inverse output of the first The first OR element is connected to the third input of the second element AND, characterized in that, in order to improve speed, a third AND element is introduced into it, the second element AND stroke connected to the second counting input (hl) -ro of the subtracting modular counter, the inequality zero output the contents of which are connected to the third input of the second OR element and to the fourth input of the second element AND, the first, second and third inputs of the second element AND are connected to the corresponding inputs of the third element AND, the fourth input of which is connected to the output of equal the zero of the contents of the J (p-D) th subtractive modular counter; the output of the third element I is connected to the third counting inputs of the position counter and the n-th subtractive modular counter. Editor M.Petrova Compiled by A. Klyuev Tehred I. Veres Proofreader V. But ha Order 5041/58 Circulation 816. Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4